Atmel AVR AT90S4434 Bedienungsanleitung

Features

•AVR®– High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 8 MIPS Throughput at 8 MHz

•Data and Nonvolatile Program Memories

– 4K/8K Bytes of In-System Programmable Flash

SPI Serial Interface for In-System Programming

Endurance: 1,000 Write/Erase Cycles

– 256/512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 256/512 Bytes Internal SRAM

– Programming Lock for Software Security

•Peripheral Features

– 8-channel, 10-bit ADC

– Programmable UART

– Master/Slave SPI Serial Interface

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare and

Capture Modes and Dual 8-, 9- or 10-bit PWM

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

•Special Microcontroller Features

– Power-on Reset Circuit

– Real-time Clock (RTC) with Separate Oscillator and Counter Mode

– External and Internal Interrupt Sources

– Three Sleep Modes: Idle, Power Save and Power-down

•Power Consumption at 4 MHz, 3V, 20°C

– Active: 6.4 mA

– Idle Mode: 1.9 mA

– Power-down Mode: <1 µA

•I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-pin PLCC and 44-pin TQFP

•Operating Voltages

–V

CC: 4.0 - 6.0V AT90S4434/AT90S8535

–V

CC: 2.7 - 6.0V AT90LS4434/AT90LS8535

•Speed Grades:

– 0 - 8 MHz AT90S4434/AT90S8535

– 0 - 4 MHz AT90LS4434/AT90LS8535

Rev. 1041F–10/00

8-bit

Microcontroller

with 4K/8K

Bytes In-System

Programmable

Flash

AT90S4434

AT90LS4434

AT90S8535

AT90LS8535

Preliminary

Pin Configurations

AT90S/LS4434 and AT90S/LS8535

Description

The AT90S4434/8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing pow-

erful instructions in a single clock cycle, the AT90S4434/8535 achieves throughputs approaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 1. The AT90S4434/8535 Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA DIR.

REG. PORTC

DATA REGISTER

PORTB

DATA REGISTER

PORTA

ANALOG MUX ADC

DATA REGISTER

PORTD

DATA REGISTER

PORTC

PROGRAMMING

LOGIC

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

SPI UART

STATUS

ALU

PORTB DRIVERS

PORTA DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB0 - PB7

PA0 - PA7

RESET

VCC

AVCC

AGND

AREF

GND

XTAL2

XTAL1

CONTROL

LINES

ANALOG

COMPARATOR

PD0 - PD7

PC0 - PC7

8-BIT DATA BUS

AT90S/LS4434 and AT90S/LS8535

The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times

faster than conventional CISC microcontrollers.

The AT90S4434/8535 provides the following features: 4K/8K bytes of In-System Programmable Flash, 256/512 bytes

EEPROM, 256/512 bytes SRAM, 32 general-purpose I/O lines, 32 general-purpose working registers, Real-time Clock

(RTC), three flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART,

8-channel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial port and three software-

selectable power-saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and

interrupt system to continue functioning. The Power-down Mode saves the register contents but freezes the oscillator, dis-

abling all other chip functions until the next interrupt or hardware reset. In Power Save Mode, the timer oscillator continues

to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-chip ISP Flash allows the

program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory

programmer. By combining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic chip, the Atmel

AT90S4434/8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded

control applications.

The AT90S4434/8535 AVR is supported with a full suite of program and system development tools including: C compilers,

macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.

Comparison between AT90S4434 and AT90S8535

The AT90S4434 has 4K bytes of In-System Programmable Flash, 256 bytes of EEPROM and 256 bytes of internal SRAM.

The AT90S8535 has 8K bytes of In-System Programmable Flash, 512 bytes of EEPROM and 512 bytes of internal SRAM.

Table 1 summarizes the different memory sizes for the two devices.

Pin Descriptions

VCC

Digital supply voltage

GND

Digital ground

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A

output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are

externally pulled low, they will source current if the internal pull-up resistors are activated.

Port A also serves as the analog inputs to the A/D Converter.

The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,

Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the

functions of various special features of the AT90S4434/8535 as listed on page 71.

Table 1. Memory Size Summary

Part Flash EEPROM SRAM

AT90S4434 4K bytes 256 bytes 256 bytes

AT90S8535 8K bytes 512 bytes 512 bytes

AT90S/LS4434 and AT90S/LS8535

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs,

Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Two Port C pins can alter-

natively be used as oscillator for Timer/Counter2.

The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,

Port D pins that are externally pulled low will source current if the pull-up resistors are activated.

Port D also serves the functions of various special features of the AT90S4434/8535 as listed on page 79.

The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate

a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

AVCC

This is the supply voltage pin for Port A and the A/D Converter. If the ADC is not used, this pin must be connected to VCC.

If the ADC is used, this pin must be connected to VCC via a low-pass filter. See page 61 for details on operation of the

ADC.

AREF

This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2V to AVCC must be

applied to this pin.

AGND

Analog ground. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Other-

wise, connect to GND.

AT90S/LS4434 and AT90S/LS8535

Clock Options

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an

on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used.

Figure 2. Oscillator Connections

Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.

External Clock

To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in

Figure 3.

Figure 3. External Clock Drive Configuration

Timer Oscillator

For the Timer Oscillator pins, PC6(TOSC1) and PC7(TOSC2), the crystal is connected directly between the pins. No exter-

nal capacitors are needed. The oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock signal

applied to TOSC1 goes through the same amplifier having a bandwidth of 256 kHz. The external clock signal should there-

fore be in the interval 0 Hz - 256 kHz.

XTAL2

XTAL1

GND

MAX 1 HC BUFFER

AT90S/LS4434 and AT90S/LS8535

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access

time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands

are output from the register file, the operation is executed and the result is stored back in the register file –in one clock

cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling

efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table

look-up function. These added function registers are the 16-bit X-register, Y-register and Z-register.

Figure 4. The AT90S4434/8535 AVR RISC Architecture

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register

operations are also executed in the ALU. Figure 4 shows the AT90S4434/8535 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.

This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing

them to be accessed as though they were ordinary memory locations.

2K/4K X 16

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

Watchdog

Timer

Analog to Digital

Converter

Analog

Comparator

I/O Lines

256/512 x 8

EEPROM

Data Bus 8-bit

AVR

AT90S4434/8535 Architecture

Serial

UART

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

256/512 x 8

Data

SRAM

Direct Addressing

Indirect Addressing

AT90S/LS4434 and AT90S/LS8535

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D

converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following

those of the register file, $20 - $5F.

The AVR uses a Harvard architecture concept –with separate memories and buses for program and data. The program

memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched

from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is

in-system downloadable Flash memory.

With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions

have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effec-

tively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the

usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are

executed). The 9/10-bit stack pointer (SP) is read/write-accessible in the I/O space.

The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR

architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 5. Memory Maps

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status

register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-

gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the

interrupt vector address, the higher the priority.

32 Gen. Purpose

Working Registers

64 I/O Registers

Internal SRAM

(256/512 x 8)

$0000

$001F

$005F

$0060

$015F/$025F

$0020

$000

$7FF/$FFF

Data MemoryProgram Memory

Program Flash

(2K/4K x 16)

EEPROM

(256/512 x 8)

$000

$0FF/$1FF

Data Memory

AT90S/LS4434 and AT90S/LS8535

General-purpose Register File

Figure 6 shows the structure of the 32 general-purpose working registers in the CPU.

Figure 6. AVR CPU General-purpose Working Registers

All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only

exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a

register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the regis-

ters in the register file (R16..R31). The general SBC, SUB, CP, AND and OR and all other operations between two

registers or on a single register apply to the entire register file.

As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 loca-

tions of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization

provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register in the file.

X-register, Y-register and Z-register

The registers R26..R31 have some added functions to their general-purpose usage. These registers are address pointers

for indirect addressing of the Data Space. The three indirect address registers, X, Y and Z, are defined in Figure 7.

Figure 7. X-, Y- and Z-registers

In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and

decrement (see the descriptions for the different instructions).

70Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

AT90S/LS4434 and AT90S/LS8535

ALU –Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a

single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into

three main categories: arithmetic, logical and bit functions.

In-System Programmable Flash Program Memory

The AT90S4434/8535 contains 4K/8K bytes on-chip, In-System Programmable Flash memory for program storage. Since

all instructions are 16- or 32-bit words, the Flash is organized as 2K/4K x 16. The Flash memory has an endurance of at

least 1000 write/erase cycles. The AT90S4434/8535 Program Counter (PC) is 11/12 bits wide, thus addressing the

2048/4096 program memory addresses.

See page 93 for a detailed description on Flash data downloading.

See page 10 for the different program memory addressing modes.

SRAM Data Memory

Figure 8 shows how the AT90S4434/8535 SRAM memory is organized.

Figure 8. SRAM Organization

The lower 352/608 data memory locations address the Register file, the I/O memory and the internal data SRAM. The first

96 locations address the Register file + I/O memory, and the next 256/512 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with

Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing

pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or

Z-registers.

R29

R30

R31

I/O Registers

$00

$01

$02

...

$3D

$3E

$3F

...

$0000

$0001

$0002

$001D

$001E

$001F

$0020

$0021

$0022

...

$005D

$005E

$005F

...

Data Address Space

$0060

$0061

$015E/$025E

$015F/$025F

...

Internal SRAM

AT90S/LS4434 and AT90S/LS8535

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,

Y and Z are decremented and incremented.

The 32 general-purpose working registers, 64 I/O registers and the 256/512 bytes of internal data SRAM in the

AT90S4434/8535 are all accessible through all these addressing modes.

See the next section for a detailed description of the different addressing modes.

Program and Data Addressing Modes

The AT90S4434/8535 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the pro-

gram memory (Flash) and data memory (SRAM, register file and I/O memory). This section describes the different

addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction

word. To simplify, not all figures show the exact location of the addressing bits.

Figure 9. Direct Single Register Addressing

The operand is contained in register d (Rd).

Figure 10. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

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