Atmel AVR1612 Montage- und Bedienungsanleitung

AVR1612: PDI programming driver

Features

• PDI driver for devices with PDI programming interface as target MCU’s

• PDI instruction set and timing

• Programming application example for ATAVRXPLAIN/AT90USB1287

- Chip erase

- Write and read application flash

- Write and read EEPROM

- Read and write Fuses

- Read and write lock-bits

- Read target device id

1 Introduction

The Program and Debug Interface (PDI) is an Atmel®proprietary interface for

external programming and on-chip debugging of the device.

The PDI supports high-speed programming of all Non-Volatile Memory (NVM)

spaces; Flash, EEPOM, Fuses, Lock-bits and the User Signature Row. This is

done by accessing the NVM Controller trough the PDI interface, and executing

NVM Controller commands.

The PDI is a 2-pin interface using the Reset pin for the clock input (PDI_CLK), and

the dedicated pin for data input and output (PDI_DATA).

This application note describes how to implement PDI programming. It is based on

the Atmel Xplain evaluation board and clarifies the protocol and timing of the PDI

programming. Please also refer to application note AVR1907: Xplain Hardware

User's Guide for how to start with the kit.

The Figure 1-1 shows the Xplain PDI programming block diagram. The firmware of

the application is for the Atmel AT90USB1287 microcontroller; however it can be

easily ported to other Atmel’s chip that features USART.

Figure 1-1. Xplain PDI Programming block diagram.

AT90USB1287 ATxmega128A1

PDI

8-bit

Microcontrollers

Application Note

Rev. 8282A-AVR-11/10

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2 PDI Target Implementation

2.1 PDI Frame Format

The PDI physical layer uses a standard UART frame format. A serial frame is defined

to be one character of eight data bits with start and stop bits and an even parity bit.

In case of write collisions or parity errors a break character (all data, parity and stop

bits set low) can be sent. Please refer to the datasheet for more information about the

break character. The Figure 2-1 describes the PDI serial frame format.

Figure 2-1. PDI serial frame format.

2.2 Serial transmission and reception

The PDI physical layer is either in Transmit (TX) or Receive (RX) mode of operation.

By default it is in RX mode, waiting for a start bit.

The programmer and the PDI operate synchronously on the PDI_CLK provided by the

programmer. The dependency between the clock edges and data sampling or data

change is fixed. As illustrated in Figure 2-2, output data (either from the programmer

or from the PDI) is always set up (changed) on the falling edge of PDI_CLK, while

data is always sampled on the rising edge of PDI_CLK.

Figure 2-2. Changing and sampling of data.

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2.3 Hardware Connection with AT90USB1287’s USART

The Atmel Xplain kit uses the Atmel AT90USB1287’s USART port to implement the

PDI port’s hardware. Figure 2-3 shows the PDI hardware connection between the

AT90USB1287 to the Atmel ATxmega128A1.

Figure 2-3. Hardware connection between AT90USB1287 to ATXmega128A1.

AT90USB1287 ATXmega128A1

XCK

RXD

TXD

220R

PDI

CLK

PDI

DATA

2.4 PDI instruction set

The PDI has a small instruction set that is used for all access to the PDI itself and to

the internal interfaces. All instructions are byte instructions. Most of the instructions

require a number of byte operands following the instruction. The instructions allow for

an external programmer to access the PDI Controller, the NVM Controller and the

NVM memories. Figure 2-4 shows the PDI instructions set, while Table 2-1 shows

gives more details about each instruction.

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Figure 2-4. PDI instruction set summary.

Table 2-1. PDI Instruction Set.

PDI Command Command Description

LDS (0x00) Load data from PDIBUS Data Space using direct addressing

STS (0x40) Store data to PDIBUS Data Space using direct addressing

LD (0x20) Load data from PDIBUS Data Space using indirect addressing

ST (0x60) Store data to PDIBUS Data Space using indirect addressing

LDCS (0x80) Load data from PDI Control and Status Register Space

STCS (0xC0) Store data to PDI Control and Status Register Space

KEY (0xE0) Set Activation Key

REPEAT (0xA0) Set Instruction Repeat Counter

Note: For more information, please refer to “PDI instruction set summary” in the

“Program and Debug Interface” section of XMEGA A MANUAL

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PDI instruction usage example:

•Write a 32-bit address into PDI Controller's pointer

Pseudo Directive: ST ptr 0x12345678

PDIBUS hex code: 0x6B 0x12 0x34 0x56 0x78

NOTE ”0x6B” stands for “ST ptr” command.

•Write a value to a address with *(ptr++) instruction through the PDI Controller

Pseudo Directive: ST *(ptr++) 0xFF

PDIBUS hex code: 0x67 0xFF

NOTE ”0x67” stands for “ST *(ptr++)” command.

•Write the repeat number into PDI Controller (REPEAT command uses

BIG_ENDIAN data)

Pseudo Directive: REPEAT 0x1234

PDIBUS hex code: 0xA1 0x34 0x12

NOTE ”0xA1” stands for “REPEAT” command and 2 bytes data length.

•Load data from PDIBUS Data Space using indirect addressing

Pseudo Directive: LD *(ptr++)

PDIBUS hex code: 0x27

Then read the PDIBUS for the loading data.

NOTE ”0x27” stands for “LD *(ptr++)” command.

Please refer to “29.5.7 Instruction Set Summary” section of the XMEGA A MANUAL

for more information.

2.5 NVM Commands

The NVM commands that can be used for accessing the NVM memories from

external programming are listed in Table 2-2. This is a super-set of the commands

available for self-programming. Each command has to be loaded to the target NVM

CMD register using the PDI commands.

For external programming, the Trigger for Action Triggered Commands is to set the

CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Commands

are triggered by a direct or indirect Load instruction (LDS or LD) from the PDI (PDI

Read). The Write Triggered Commands is triggered by a direct or indirect Store

instruction (STS or ST) from the PDI (PDI Write).

Table 2-2. NVM commands available for external programming.

CMD[6:0] Commands/Operation Trigger

0x00 No Operation -

0x40 Chip Erase

(1) CMDEX

0x43 Read NVM PDI Read

Flash Page Buffer

0x23 Load Flash Page Buffer PDI Write

0x26 Erase Flash Page Buffer CMDEX

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CMD[6:0] Commands/Operation Trigger

Flash

0x2B Erase Flash Page PDI Write

0x2E Flash Page Write PDI Write

0x2F Erase & Write Flash Page PDI Write

0x78 Flash CRC CMDEX

Application Section

0x20 Erase Application Section PDI Write

0x22 Erase Application Section Page PDI Write

0x24 Write Application Section Page PDI Write

0x25 Erase & Write Application Section Page PDI Write

0x38 Application Section CRC CMDEX

Boot Loader Section

0x68 Erase Boot Section PDI Write

0x2A Erase Boot Loader Section Page PDI Write

0x2C Write Boot Loader Section Page PDI Write

0x2D Erase & Write Boot Loader Section Page PDI Write

0x39 Boot Loader Section CRC NVMAA

Calibration and User Signature sections

0x03 Read User Signature Row PDI Read

0x18 Erase User Signature Row PDI Write

0x1A Write User Signature Row PDI Write

0x02 Read Calibration Row PDI Read

Fuses and Lock Bits

0x07 Read Fuse PDI Read

0x4C Write Fuse PDI Write

0x08 Write Lock Bits CMDEX

EEPROM Page Buffer

0x33 Load EEPROM Page Buffer PDI Write

0x36 Erase EEPROM Page Buffer CMDEX

EEPROM

0x30 Erase EEPROM CMDEX

0x32 Erase EEPROM Page PDI Write

0x34 Write EEPROM Page PDI Write

0x35 Erase & Write EEPROM Page PDI Write

0x06 Read EEPROM PDI Read

Notes: For more information, please refer the “External Programming” section of XMEGA A

MANUAL

1. If the EESAVE fuse is programmed the EEPROM is preserved during chip erase.

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3 The Programming Interface

The PDI low level driver layer handles the basic interface to the USART driver. The

physical layer uses a bi-directional half-duplex synchronous serial receiver and

transmitter (as a USART in USART mode). The physical layer includes start-of-frame

detection, frame error detection, parity generation, parity error detection, and collision

detection. The PDI is accessed through two pins. Table 3-1 shows the PDI interface

checklist.

Table 3-1. PDI port interface checklist.

Signal name Recommended pin connection Description

PDI_CLK

A reset pull-up should be 10k or weaker, or be removed altogether.

Any reset decoupling capacitors should be removed if PDI programming and

debugging is used.

Other external reset sources driving this line should be disconnected.

(Any load on the clock line may give a delay on the clock edge that causes

data bit to sampled/generated too late and result in communication failure.)

PDI_CLK: clock input/Reset pin

(internally pulled-up)

PDI_DATA Connect to programming header/test point only

PDI_DATA: PDI data input/output

(internally pulled-down)

In addition to these two pins, VCC and GND must also be connected between the

External Programmer/debugger and the device. Figure 3-1 shows a typical

connection.

Figure 3-1. PDI connection.

3.1 Overview of the PDI programming process

The process of the PDI programming is shown below:

1. Enable the PDI module.

2. Enter external programming mode.

3. Program or read the memory (Flash/EEPROM /Fuses/Lock-bits) with PDI.

4. Exit the PDI programming mode.

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3.2 Enable the PDI module

The PDI Physical must be enabled before it can be used. This is done by first forcing

the PDI_DATA line high for a period longer than the equivalent external reset

minimum pulse width (refer to device data sheet for reset characteristics).

The first PDI_CLK cycle must start no later than 100µS after the RESET functionality

of the Reset pin was disabled. If this does not occur in time the RESET functionality

of the Reset pin is automatically enabled again and the enabling procedure must start

over again.

After this sequence, the PDI is enabled and ready to receive instructions. The enable

sequence is shown in Figure 3-2.

Figure 3-2. Sequence for enabling the PDI.

3.3 Enter external programming mode

Even after an external programmer has established communication with the PDI

module, the internal interfaces are not accessible by default. To get access to the

NVM Controller and the NVM memories for programming, a unique key must be

signalized by using the KEY instruction. The internal interface is accessed as one

linear address space using a dedicated bus (PDIBUS) between the PDI and the

internal interfaces.

PDI Control and Status Register Space can be accessed with STCS (Store) and

LDCS (Load) instruction. Please refer to “29.7 Register Description - PDI Control and

Status Register” section and “29.5.7 Instruction Set Summary” section of the XMEGA

A MANUAL for more information.

The key that must be sent using the KEY instruction is 64 bits long. The key that will

enable NVM Programming is:

0x1289AB45CDD888FF

The sequence of entering external programming is as following:

1. Load the PDI RESET register with the Reset Signature (0x59).

2. Load the correct NVM key in the PDI.

3. Poll NVMEN in the PDI Status Register (PDI STATUS) until NVMEN is set.

When the NVMEN bit in the PDI STATUS register is set the NVM interface is active

from the PDI.

3.4 Memory Programming

This section describes how to program the Non Volatile Memory (NVM) in XMEGA®

with external programming. The NVM consist of the Flash Program Memory, User

Signature and Calibration rows, Fuses and Lock Bits, and EEPROM data memory.

For external programming the device is accessed through the PDI and PDI Controller,

using PDI physical connection. Through the PDI, the external programmer access all

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NVM memories and NVM Controller using the PDI Bus. Doing this all data and

program memory spaces are mapped into the linear PDI memory space.

Figure 3-3 shows the PDI memory space and the base address for each memory

space in the Atmel ATxmega128A1.

Figure 3-3. Memory map for PDI accessing the data and program memories.

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3.4.1 Chip Erase

The Chip Erase command is used to erase the Flash Program Memory, EEPROM

and Lock-Bits. The User Signature Row, Calibration Row and Fuses are not affected.

The Chip Erase sequence is as below:

1. Load the NVM CMD register with Chip Erase command (refer to Table 2-2).

2. Set the CMDEX bit in NVM CTRLA register.

NOTE The Chip Erase command disables the PDI controller and the NVM. Poll the NVMEN

bit until this is set, indict the PDI controller is enabled.

3.4.2 Program Flash and EEPROM Page

Flash and EEPROM page programming is done by first filling the associated page

buffer, and then writing the entire page buffer to a selected page in Flash or

EEPROM.

The size of the page buffers depend on the Flash and EEPROM size in each device,

and details on page size and page number is described in each device data sheet.

3.4.2.1 Flash and EEPROM Programming Sequence

Before programming a Flash or EEPROM page with the data in the Flash or

EEPROM page buffer, the Flash or EEPROM page must be erased. Programming an

un-erased Flash or EEPROM Page will corrupt the content in the Flash or EEPROM

Page.

1. Erase Flash or EEPROM Page Buffer.

2. Load the Flash or EEPROM Page Buffer.

3. Perform a Page Erase and Write.

3.4.2.2 Erase Page Buffer

The Erase Flash Page Buffer and Erase EEPROM Page Buffer commands are used

to erase the Flash and EEPROM page buffers.

1. Load the NVM CMD register with the Erase Flash/EEPROM Page Buffer

command.

2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP

sequence during self-programming.

The BUSY flag in the NVM STATUS register will be set until the operation is

completed.

3.4.2.3 Load Page Buffer

The Load Flash Page Buffer and Load EEPROM Page Buffer commands are used to

load one byte of data into the Flash and EEPROM page buffers.

1. Load the NVM CMD register with the Load Flash/EEPROM Page Buffer

command.

2. Write the selected memory address by doing a PDI Write operation.

Since the Flash page buffer is word accessing and the PDI uses byte addressing, the

PDI must write the Flash Page Buffer in correct order.

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