Compaq ProLiant 8500 Bedienungsanleitung

TECHNOLOGYBRIEF

TC000604TB

June 2000

Compaq Computer

Corporation

ISSD Technology

Communications

CONTENTS

Introduction........................3

High-Performance

Technologies ......................3

ProLiant 8500 Architecture.......4

Pentium III Xeon

Processor Technology............10

High-Availability

Technologies .................... 12

PCI Hot Plug Technology.......12

Redundant Network Interface

Controller Technology............13

Redundant Hot-Plug Fans......13

Redundant Processor

Power Modules......................14

Redundant Hot-Plug

Power Supplies .....................15

Hot-Plug Hard Disk Drives......17

Auto Processor

Bus Recovery........................17

Storage

Technologies .................... 17

Hard Drive Technology...........17

Integrated Array

Controller Technology............18

Management

Technologies .................... 19

Remote-Flash

Redundant ROM....................20

Auto-Default ROM

Configuration.........................20

Integrated Management

Display..................................21

Integrated Remote Console....21

Remote Insight

Board/PCI Option ..................21

Serviceability

Features............................ 22

Conclusion........................ 23

Compaq ProLiant 8500 Server Technology

This technology brief describes the high-performance, high-availability, storage, and

management technologies built into the Compaq ProLiant 8500 server. The high-

performance technologies include a new 8-way system architecture driven by the

Profusion chipset codeveloped by Compaq, Intel, and Corollary, as well as Intel’s

Pentium III Xeon processors. In addition, new disk drive technology and a new

integrated array controller optimize the ProLiant 8500 server’s internal storage for

operating system and boot support while allowing maximum external storage capacity.

The high-availability technologies include PCI Hot Plug technology; redundant hot-plug

power supplies, drives, and fans; redundant processor power modules; and auto

processor bus recovery. The ProLiant 8500 server uses a highly modular design that

allows easy access to components, thus reducing downtime for service and upgrades.

The ProLiant 8500 server also incorporates key management technologies, such as the

Integrated Remote Console, Integrated Management Display, Remote-flash Redundant

ROM, and auto-default ROM configuration, that further enhance availability.

The intended audience for this paper is engineers and system administrators familiar

with existing Compaq technology and servers. For those less familiar with Compaq

technology, please see the related technology briefs referenced in this document. For

more information about the ProLiant 8500 server, see the complete list of features at

http://www.compaq.com/products/servers/ProLiant8500/quickspecs.html.

Please direct comments regarding this communication to the ISSD Technology Communications Group at this Internet

address: Te[email protected]m

TECHNOLOGY BRIEF (cont.)

TC000604TB

NOTICE

The information in this publication is subject to change without notice and is provided “AS IS”

WITHOUT WARRANTY OF ANY KIND. THE ENTIRE RISK ARISING OUT OF THE USE

OF THIS INFORMATION REMAINS WITH RECIPIENT. IN NO EVENT SHALL COMPAQ

BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, SPECIAL, PUNITIVE

OR OTHER DAMAGES WHATSOEVER (INCLUDING WITHOUT LIMITATION,

DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION OR LOSS OF

BUSINESS INFORMATION), EVEN IF COMPAQ HAS BEEN ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES.

The limited warranties for Compaq products are exclusively set forth in the documentation

accompanying such products. Nothing herein should be construed as constituting a further or

additional warranty.

This publication does not constitute an endorsement of the product or products that were tested.

The configuration or configurations tested or described may or may not be the only available

solution. This test is not a determination of product quality or correctness, nor does it ensure

compliance with any federal state or local requirements.

Compaq, Contura, Deskpro, Fastart, Compaq Insight Manager, LTE, PageMarq, Systempro,

Systempro/LT, ProLiant, TwinTray, ROMPaq, LicensePaq, QVision, SLT, ProLinea, SmartStart,

NetFlex, DirectPlus, QuickFind, RemotePaq, BackPaq, TechPaq, SpeedPaq, QuickBack, PaqFax,

Presario, SilentCool, CompaqCare (design), Aero, SmartStation, MiniStation, and PaqRap,

ProSignia, Concerto, Vocalyst, and MediaPilot are registered with the United States Patent and

Trademark Office.

Change is Good, Compaq Capital, Colinq, Armada, SmartQ, Counselor, CarePaq, Netelligent,

Smart Uplink, Extended Repeater Architecture, Scalable Clock Architecture, QuickChoice,

Systempro/XL, Net1, LTE Elite, PageMate, SoftPaq, FirstPaq, SolutionPaq, EasyPoint, EZ Help,

MaxLight, MultiLock, QuickBlank, QuickLock, UltraView, Innovate logo, and Compaq PC Card

Solution logo are trademarks and/or service marks of Compaq Computer Corporation.

Microsoft, Windows, Windows NT, Windows NT Advanced Server, SQL Server for Windows NT

are trademarks and/or registered trademarks of Microsoft Corporation.

NetWare and Novell are registered trademarks and IntranetWare, NDS, and Novell Directory

Services are trademarks of Novell, Inc.

Pentium is a registered trademark and Xeon is a trademark of Intel Corporation.

Other product names mentioned herein may be trademarks and/or registered trademarks of their

respective companies.

Compaq ProLiant 8500 Server Technology

Second Edition (June 2000)

Document Number TC000604TB

TECHNOLOGY BRIEF (cont.)

TC000604TB

INTRODUCTION

In today’s business environment, enterprise customers require powerful servers with fault-tolerant

features to keep their businesses running 24 hours a day, 7 days a week. They also need servers

that are easy to manage and will scale to meet future requirements.

The Compaq ProLiant 8500 server delivers outstanding 8-way scalable performance for 24x7

multiserver rack environments. Performance is maximized with up to eight Intel Pentium III Xeon

processors and 16 GB of synchronous dynamic random access memory (SDRAM). Input/output

(I/O) performance is further enhanced by eleven 64-bit PCI slots—two at 66 MHz—an integrated

array controller, and Wide Ultra-3 SCSI hard drives.

High-availability features include PCI Hot Plug slots, redundant hot-pluggable power supplies,

redundant hot-pluggable fans, redundant processor power modules (PPMs), and redundant network

interface controllers (NICs). The ProLiant 8500 server includes server management and

configuration tools that further enhance availability, such as Remote-flash Redundant ROM and

Integrated Remote Console (IRC). Additionally, a highly modular design and System Interconnect

Status Indicators improve serviceability and further reduce downtime associated with upgrades and

field maintenance.

This technology brief explains the features of the ProLiant 8500 server and describes the

management and storage technologies that enhance performance and availability. Many of these

technologies are covered in more detail in separate technology briefs, which are referenced in this

document.

HIGH-PERFORMANCE TECHNOLOGIES

The Compaq ProLiant 8500 server is a powerful, industry-leading technology solution for

distributed enterprise computing. A revolutionary new 8-way system architecture allows the

ProLiant 8500 server to deliver unsurpassed performance. This new architecture is the first

implementation in the industry of the Profusion chipset and features Pentium III Xeon processors.

Compaq servers using this architecture provide new levels of performance without requiring

modifications or special releases of operating systems (OSs) or applications. The Compaq 8-way

architecture provides nearly linear scalability for up to eight processors running under Microsoft

Windows NT 4.0, Microsoft Windows 2000, Novell NetWare, or SCO UnixWare. The 8-way

architecture delivers superior performance and price:performance for processor-intensive

applications such as Microsoft Terminal Server and Oracle databases; for memory-intensive

applications such as Lotus Notes, Microsoft Exchange, and SAP solutions; and for I/O-intensive

applications such as Microsoft SQL Server.

ROM – read only memory

PCI – peripheral

component interconnect

SCSI – small computer

system interface

TECHNOLOGY BRIEF (cont.)

TC000604TB

ProLiant 8500 Architecture

The system architecture is the key to the high level of performance offered by the ProLiant 8500

server. Compaq worked closely with Intel and Corollary for three years to perfect the 8-way

symmetric multiprocessing (SMP) architecture so that the processors, memory, and I/O subsystem

work in harmony to deliver breakthrough levels of performance. Figure 1 illustrates the

architecture used in the ProLiant 8500 server. The essential features of the architecture include:

•Profusion five-point crossbar switch

•Dual 100-MHz processor buses

•Dual 100-MHz memory buses, each with its own memory controller

•Dedicated 100-MHz I/O bus

•Support for up to eight Pentium III Xeon processors

•Support for up to 16 GB of two-way, cache-line interleaved SDRAM

•Dual cache accelerators

•I/O filter

•Three Compaq designed host-to-PCI bridges

Figure 1: Block diagram of the ProLiant 8500 system architecture.

TECHNOLOGY BRIEF (cont.)

TC000604TB

Profusion Chipset

At the heart of the 8-way architecture is the Profusion chipset. The chipset uses a five-point

crossbar switch (Figure 2) to connect processor buses, memory ports, and the I/O bus. The

crossbar switch contains static random access memory (SRAM) with ten ports—five read and five

write—that appear as five bidirectional ports, one for each of the processor, memory, and I/O

buses. The switch may connect two ports directly or may store data from the originating bus in the

SRAM before it is transferred to the destination bus. This nonblocking design allows simultaneous

read and write accesses from all five buses, which results in better system performance.

10-Port SRAM

I/O Interface

Memory Interface Memory Interface

Processor Interface

Right Processor Bus

Left Processor Bus

I/O Bus

Right Memory PortLeft Memory Port

Figure 2: Block diagram of the Profusion crossbar switch.

The Profusion crossbar switch provides direct paths from each memory bus to each processor bus

and to the I/O bus. Depending on the status of the system, the direct paths can be used to bypass

the SRAM, thus reducing latency and improving performance. The direct paths are used only to

read data. To improve processor utilization and performance, write data is always posted to the

SRAM and written to main memory later.

The Profusion crossbar switch consists of two physical chips—the memory address controller

(MAC) and the data interface buffer (DIB). This functional partitioning of the application-specific

integrated circuit (ASIC), as shown in Figure 3, improves system performance. For every

transaction from a processor or an I/O controller, the address and command portions are routed

through the MAC and the data is routed through the DIB. The MAC manages the external cache

accelerators and tracks the information stored in the DIB. The DIB allows simultaneous data

transfer on all five ports, has 64-cache-line buffers, and uses error-correcting code to maintain data

integrity. The cache-line buffers can be used by any transaction for any device on any bus; and

since there are no dedicated queues between buses, the efficiency of the buffers is high. This

improves system performance.

TECHNOLOGY BRIEF (cont.)

TC000604TB

Processor

bus

Cache

Accelerator

Processor

bus

address

data

address

data

Memory

Array

Memory

Array

I/O bus data address

Memory Access

Controller (MAC)

Data Interface

Buffer (DIB)

address

Cache

Accelerator

Figure 3: ASIC partitioning in the Profusion chipset.

Processor and I/O Buses

The ProLiant 8500 server includes two 64-bit processor buses and a dedicated 64-bit I/O bus. All

three are 100-MHz advanced Gunning transceiver logic plus (AGTL+) buses with a theoretical

maximum throughput of 800 MB/s. AGTL+ buses facilitate higher clock speeds without

significantly reducing the bus length or number of electrical loads. Each 100-MHz AGTL+ bus

can support a maximum of five loads per bus. This allows four processors and one connection to

the memory controller on each processor bus. The use of two processor buses enables the ProLiant

8500 server to support up to eight Pentium III Xeon processors.

The Profusion chipset joins the two processor buses, the I/O bus, and the two memory ports. The

otherwise independent processor and I/O buses are joined by a logical connection that is made only

when required to transfer data. Each of the three AGTL+ buses has independent access to the two

memory ports. This architecture prevents I/O traffic from consuming bandwidth on the processor

bus. In addition, the use of 100-MHz buses and five independent paths allows the crossbar switch

to deliver an aggregate instantaneous peak throughput of 4 GB/s—unprecedented high performance

for customers.

Memory Subsystem

The ProLiant 8500 memory subsystem includes dual 100-MHz buses, each with its own memory

controller. The use of two memory buses increases memory bandwidth, reduces access conflicts,

and increases the quantity of memory supported. Memory attached to each of the buses is cache-

line interleaved, which means the buses share a common address range. One memory bus responds

to even-numbered cache lines, and the other bus responds to odd-numbered cache lines. This

configuration allows simultaneous use of both memory buses, which theoretically doubles

throughput. It is especially advantageous for applications that access memory randomly. In

random accesses, roughly half the requests at any one time are even-numbered lines, while the other

half are odd-numbered lines.

TECHNOLOGY BRIEF (cont.)

TC000604TB

The memory subsystem uses uniform memory access, which reduces latency and gives all

processors equal access times to either memory bus. In systems using nonuniform memory access

architectures, a processor has quick access to one memory bus but incurs a lag time (or latency)

when accessing a second memory bus.

The ProLiant 8500 server supports up to 16 GB of error checking and correcting SDRAM that

corrects all single-bit errors and detects double-bit errors. Memory is divided into eight banks,

each consisting of two dual inline memory modules.

Although the Profusion chipset supports up to 32 GB of memory, industry-standard OSs provide

only minimal support and scalability for this memory capacity, and enhanced support will not be

available for an extended period. Also, in discussions with customers, Compaq learned that very

few server implementations are fully configured with memory. With this in mind, Compaq used the

internal server space to provide additional drive capacity in the ProLiant 8500 server. As customer

requirements and OS capabilities increase in the future, Compaq will continue to modify servers to

match these requirements.

Cache Accelerators

One of the main challenges of designing an efficient SMP architecture is maintaining cache

coherency. To allow faster access to memory, most processors write data to cache memory rather

than main memory. When a processor writes data to its cache, that cache has a newer copy of the

data than main memory. Cache coherency ensures that the most recent copy of the data is read by

any device that requests it. The cache coherency protocol essentially makes the cache look like

main memory. Cache coherency is critical for the proper operation of an SMP architecture, and the

performance and scalability of the architecture is affected by how efficiently it maintains cache

coherency.

With multiple processor buses and a separate I/O bus, it is extremely challenging to maintain cache

coherency in the 8-way architecture. Each memory access must look at, or snoop, the caches on its

local processor bus and snoop all caches on the remote processor bus and the I/O bus. The amount

of snoop traffic can significantly impact the scalability of the system.

The ProLiant 8500 architecture uses cache accelerators to minimize snoop traffic to the remote

processor bus and I/O bus. The cache accelerators store the address and state of the data for all

caches on their respective buses. The Profusion crossbar switch uses this information to determine

whether to snoop the remote processor and I/O buses. Depending on how often a software

application shares data, the reduction in snoop traffic can significantly improve overall system

performance and scalability.

I/O Filter

The ProLiant 8500 server also includes three Compaq host-to-PCI bridges with prefetch buffers, so

they act as caching bridges. The Profusion chipset contains a built-in I/O filter for the caching

bridges on the I/O bus. The I/O filter enhances performance by reducing snoop traffic on the I/O

bus. This I/O filter is designed to work with all three of the Compaq host-to-PCI bridges. When a

processor requests a cache line with the intent to modify it, the MAC performs a lookup into the

I/O filter to determine if that line resides in one of the caching bridges. If it does reside there, the

MAC initiates a transaction on the I/O bus to invalidate that cache line. If the cache line is not

present in one of the bridges, then no transaction is run on the bus.

TECHNOLOGY BRIEF (cont.)

TC000604TB

Compaq Host-to-PCI Bridges

The Compaq host-to-PCI bridges included in the ProLiant 8500 server were engineered to enhance

performance of the Profusion chipset. They include the following features:

•64-bit, 66-MHz PCI support with a theoretical peak throughput of 533 MB/s

•Delayed transaction support

•Asynchronous design to accommodate multiple bus frequencies

•Multiple prefetch buffers

•PCI Hot Plug technology

•Peer-to-peer transaction support

64-Bit, 66-MHz PCI Support

Compaq licensed the host-to-PCI bridges to Intel, and they will ship with a Compaq logo on top in

servers produced by other original equipment manufacturers. They are compliant with the PCI 2.2

Specification1and support 64-bit, 66-MHz PCI transactions.

The ProLiant 8500 supports three bridges with up to eleven I/O expansion slots. PCI Bus 1

operates at 33 MHz and includes three 64-bit PCI Hot Plug slots. PCI Bus 2 is also a 33-MHz bus

and includes six 64-bit PCI Hot Plug slots. PCI Bus 3 operates at 66 MHz with two 64-bit PCI Hot

Plug slots. Each of the 33-MHz buses has a maximum throughput of 267 MB/s. The 66-MHz bus

has a maximum throughput of 533 MB/s. This combination of 11 slots provides adequate I/O

bandwidth for the most demanding applications.

The Compaq 8-way architecture will support up to four Compaq host-to-PCI bridges. However, by

incorporating only three host-to-PCI bridges, the ProLiant 8500 server has room on the I/O board

to deliver an additional PCI slot, a meaningful advantage for enterprise customers who consistently

request additional capacity.

Delayed Transactions

One of the most important features of Compaq’s host-to-PCI bridge is that it supports delayed PCI

transactions, which improve bus performance. In a delayed PCI transaction, the device that

initiates the transaction polls the host-to-PCI bridge to determine if the requested data is there,

rather than holding the bus while waiting for the data. This allows other devices to use the bus

while the transaction is completed. To further improve bus efficiency, Compaq built in additional

features to reduce the amount of polling.

Asynchronous Design

The bridge is split into two sections: upstream (host I/O side) and downstream (PCI side). All the

functions on the upstream side are in the host processor clock domain at 100 MHz. All functions

on the downstream side are in the PCI clock domain at up to 66 MHz. This asynchronous design is

a flexible solution for supporting multiple clock speeds.

Multiple Prefetch Buffers

The Compaq host-to-PCI bridge is designed with multiple prefetch buffers to ensure optimum I/O-

to-processor performance. Each buffer can hold multiple cache lines. These buffers are sized to

provide optimal performance at a reasonable and cost-effective die size. Because of the delayed

transaction support, the bridge can get data for multiple PCI devices concurrently. Other

controllers can hold only a single cache line and a single request at a time.

1PCI Local Bus Specification, Revision 2.2, announced January 25, 1999, PCI Special Interest

Group.

TECHNOLOGY BRIEF (cont.)

TC000604TB

PCI Hot Plug Technology

The host-to-PCI bridges include electronics to support PCI Hot Plug technology, which was

pioneered by Compaq. PCI Hot Plug technology provides the ability to remove, replace, upgrade,

and add PCI adapters without shutting down the server. Any PCI adapter can be placed in a PCI

Hot Plug slot; however, PCI Hot Plug device drivers and OS support are required to enable PCI

Hot Plug functionality.

Peer-to-Peer Transactions

The host-to-PCI bridges also support PCI peer-to-peer transactions. They allow communications

between two devices on the same PCI bus segment. They also allow communication across the I/O

bus between PCI devices on different PCI bus segments (Figure 4).

PCI Device 1

Host-to-PCI Bridge

I/O 100 MHz Bus

Processor Bus

PCI Bus

Host-to-PCI Bridge

PCI Device 2

PCI Device 3

PCI Device 4

PCI Bus

PCI Device 5

Figure 4: Schematic of peer-to-peer communications between PCI devices on different I/O bus segments.

Microprocessors embedded in the PCI devices make these devices “intelligent” and perform the

communication tasks otherwise handled by the processors. Thus, the host-to-PCI bridges enhance

performance by freeing the system processors to do other work.

TECHNOLOGY BRIEF (cont.)

TC000604TB

Pentium III Xeon Processor Technology

The Pentium III Xeon processor is based on the Pentium II Xeon processor cartridge form factor.

The Pentium III Xeon processor provides a higher internal core frequency than the Pentium II

Xeon processor and includes 70 new streaming instructions that permit more efficient use of

memory above 4 GB. The Pentium III Xeon processor includes the following features:

•Minimum core frequency of 550 MHz

•330-contact slot connector form factor (formerly called Slot 2)

•Full-speed cache on module

•512-KB (550-MHz core frequency only), 1-MB, or 2-MB Level 2 (L2) cache

•Katmai core logic

Level 2 Cache

Each Pentium III Xeon processor includes an L2 cache sized at 512 KB, 1 MB, or 2 MB that

operates on a full-speed backside bus. The large cache size and full-speed backside bus enable

very efficient access to the most frequently used data. This reduces traffic on the host bus and

notably enhances performance.

Katmai Core Logic

Aside from speed and cache size increases, the main difference between the Pentium II Xeon and

Pentium III Xeon processors is the migration to the Katmai core logic. The Katmai core logic adds

the following enhancements to the existing Intel core:

•Memory streaming

•Concurrent Single Instruction Multiple Data – Floating Point (SIMD-FP)

•Katmai New Instructions (KNI)

Memory Streaming

Memory streaming is a set of techniques that increase the utilization of the memory bus during

memory reads and writes. Processors must frequently wait for data not stored in cache memory to

be retrieved from system memory. Because the system bus connecting the memory to the processor

is slower than the processor core speed, this results in a performance bottleneck. Katmai’s memory

streaming enables the processor to prefetch data from system memory to cache memory.

During writes to memory, other new instructions can tell the processor to bypass the L2 cache and

write data directly back to memory. Bypassing the L2 cache frees room in the cache for more data.

This technique is useful when the software programmer knows in advance that the data will not be

requested again in the near future.

Concurrent SIMD-FP

Concurrent SIMD-FP applies the same architecture used by MMX for integer operations to

floating-point numbers. Floating-point numbers are used extensively in 3D graphics and scientific

computations. Katmai processors have eight new registers that can each hold four single-precision

floating-point numbers. Once the registers are filled, a single instruction can be used to add,

subtract, or do other operations between the registers. For example, eight floating-point numbers

could be added together using one instruction call.

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