Cypress Semiconductor CY7C130 Bedienungsanleitung

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

1K x 8 Dual-Port Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 38-06002 Rev. *E Revised December 09, 2008

Features

■

True dual-ported memory cells, which allow simultaneous

reads of the same memory location

■

1K x 8 organization

■

0.65 micron CMOS for optimum speed and power

■

High speed access: 15 ns

■

Low operating power: I

= 110 mA (maximum)

■

Fully asynchronous operation

■

Automatic power down

■

Master CY7C130/130A/CY7C131/131A easily expands data

bus width to 16 or more bits using slave CY7C140/CY7C141

■

BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY

input on CY7C140/CY7C141

■

INT flag for port-to-port communication

■

Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,

52-pin TQFP

■

Pb-free packages available

Functional Description

The CY7C130/130A/CY7C131/131A/CY7C140

[1]

and CY7C141

are high speed CMOS 1K by 8 dual-port static RAMs. Two ports

are provided permitting independent access to any location in

memory. The CY7C130/130A/ CY7C131/131A can be used as

either a standalone 8-bit dual-port static RAM or as a master

dual-port RAM in conjunction with the CY7C140/CY7C141 slave

dual-port device in systems requiring 16-bit or greater word

widths. It is the solution to applications requiring shared or

buffered data, such as cache memory for DSP, bit-slice, or multi-

processor designs.

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). Two flags are provided

on each port, BUSY and INT. BUSY signals that the port is trying

to access the same location currently being accessed by the

other port. INT is an interrupt flag indicating that data is placed

in a unique location (3FF for the left port and 3FE for the right

port). An automatic power down feature is controlled indepen-

dently on each port by the chip enable (CE) pins.

The CY7C130/130A and CY7C140 are available in 48-pin DIP.

The CY7C131/131A and CY7C141 are available in 52-pin

PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free

PQFP.

R/W

BUSY

R/W

I/O

BUSY

INT

ARBITRATION

LOGIC

(7C130/7C131 ONLY)

AND

INTERRUPT LOGIC

CONTROL

I/O CONTROL

I/O

MEMORY

ARRAY ADDRESS

DECODER

ADDRESS

DECODER

[2]

[3] [3]

Logic Block Diagram

Notes

1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.

2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.

CY7C140/CY7C141 (Slave): BUSY is input.

3. Open drain outputs: pull-up resistor required.

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 2 of 19

Pin Configurations

Figure 1. Pin Diagram - DIP (Top View)

Figure 2. Pin Diagram - PLCC (Top View) Figure 3. Pin Diagram - PQFP (Top View)

23 26

24 25

GND

11 38

12 37

R/W

BUSY

INT

I/O

R/W

BUSY

INT

I/O

7C130

7C140

VCC

2122 23 24 25 26 27 28 29 30 31 32 33

7 6 5 4 3 2 52 51 50 49 48 47

I/O

GND

BUSY

INT

R/W

BUSY

INT

CER

7C131

7C141

1415 16 17 18 19 20 21 22 23 24 25 26

52 5150 49 48 47 45 44 43 42 41 40

VCC

BUSY

INT

R/W

BUSY

INT

CER

I/O

GND

7C131

7C141

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 3 of 19

Pin Definitions

Left Port Right Port Description

Chip Enable

R/W

Read/Write Enable

Output Enable

–A

11/12L

–A

11/12R

Address

I/O

–I/O

15/17L

I/O

–I/O

15/17R

Data Bus Input/Output

INT

Interrupt Flag

BUSY

Busy Flag

Power

GND Ground

Selection Guide

Parameter 7C131-15

[4]

7C131A-15

7C141-15 7C131-25

[4]

7C141-25

7C130-30

7C130A-30

7C131-30

7C140-30

7C141-30

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45

7C131-45

7C140-45

7C141-45

7C130-55

7C131-55

7C140-55

7C141-55 Unit

Maximum Access Time 15 25 30 35 45 55 ns

Maximum Operating

Current Com’l/Ind 190 170 170 120 120 110 mA

Maximum Standby

Current Com’l/Ind 75 65 65 45 45 35 mA

Shaded areas contain preliminary information.

Note

4. 15 and 25 ns version available only in PLCC/PQFP packages.

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 4 of 19

Maximum Ratings

[5]

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Storage Temperature ................................. –65°C to +150

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage to Ground Potential

(Pin 48 to Pin 24)............................................–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State................................................–0.5V to +7.0V

DC Input Voltage ............................................–3.5V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch Up Current.................................................... >200 mA

Operating Range

Range Ambient Temperature V

Commercial 0

C to +70

C 5V ± 10%

Industrial –40

C to +85

C 5V ± 10%

Military

[6]

–55

C to +125

C 5V ± 10%

Electrical Characteristics Over the Operating Range

[7]

Parameter Description Test Conditions

7C131-15

[4]

7C131A-15

7C141-15

7C130-30

[4]

7C130A-30

7C131-25,30

7C140-30

7C141-25,30

7C130-35,45

7C131-35,45

7C140-35,45

7C141-35,45

7C130-55

7C131-55

7C140-55

7C141-55 Unit

Min Max Min Max Min Max Min Max

Output HIGH Voltage V

= Min, I

= –4.0 mA 2.4 2.4 2.4 2.4 V

Output LOW Voltage I

= 4.0 mA 0.4 0.4 0.4 0.4 V

= 16.0 mA

[8]

0.5 0.5 0.5 0.5

Input HIGH Voltage 2.2 2.2 2.2 2.2 V

Input LOW Voltage 0.8 0.8 0.8 0.8 V

Input Leakage Current GND < V

< V

–5 +5 –5 +5 –5 +5 –5 +5 μA

Output Leakage

Current GND < V

Output Disabled –5 +5 –5 +5 –5 +5 –5 +5 μA

Output Short

Circuit Current

[9, 10]

= Max,

OUT

= GND –350 –350 –350 –350 mA

Operating

Supply Current CE = V

Outputs Open, f = f

MAX[11]

Com’l 190 170 120 110 mA

SB1

Standby Current

Both Ports, TTL Inputs CE

and CE

> V

f = f

MAX[11]

Com’l 75 65 45 35 mA

SB2

Standby Current

One Port,

TTL Inputs

or CE

> V

Active Port Outputs Open

f = f

MAX[11]

Com’l 135 115 90 75 mA

SB3

Standby Current

Both Ports,

CMOS Inputs

BothPortsCE

and CE

– 0.2V,

> V

– 0.2V

or V

< 0.2V, f = 0

Com’l 15 15 15 15 mA

SB4

Standby Current

One Port,

CMOS Inputs

One Port CE

– 0.2V,

> V

– 0.2V

or V

< 0.2V,

ActivePortOutputsOpen,f=

MAX[11]

Com’l 125 105 85 70 mA

Shaded areas contain preliminary information.

Notes

5. The voltage on any input or I/O pin cannot exceed the power pin during power up.

6. T

is the “instant on” case temperature

7. See the last page of this specification for Group A subgroup testing information.

8. BUSYand INT pins only.

9. Duration of the short circuit should not exceed 30 seconds.

10.This parameter is guaranteed but not tested.

11. At f = f

MAX

, address and data inputs are cycling at the maximum frequency of read cycle of 1/t

and using AC Test Waveforms input levels of GND to 3V.

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 5 of 19

Capacitance

[10]

Parameter Description Test Conditions Max Unit

Input Capacitance T

= 25°C, f = 1 MHz,

= 5.0V 15 pF

OUT

Output Capacitance 10 pF

Figure 4. AC Test Loads and Waveforms

3.0V

OUTPUT

R1 893Ω

347Ω

30 pF

INCLUDING

JIGAND

SCOPE

GND 90% 90%

10%

≤5ns ≤5ns

OUTPUT

R1 893Ω

347Ω

5pF

INCLUDING

JIGAND

SCOPE

(a) (b)

OUTPUT 1.40V

Equivalent to: THÉVENIN EQUIVALENT

281Ω

BUSY

INT

BUSY Output Load

(CY7C130/CY7C131 ONLY)

10%

ALL INPUT PULSES

250Ω

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 6 of 19

Switching Characteristics

Over the Operating Range

[7, 12]

Parameter Description

7C131-15

[4]

7C131A-15

7C141-15

7C130-25

[4]

7C131-25

7C140-25

7C141-25

7C130-30

7C130A-30

7C131-30

7C140-30

7C141-30 Unit

Min Max Min Max Min Max

Read Cycle

Read Cycle Time 15 25 30 ns

Address to Data Valid

[13]

15 25 30 ns

OHA

Data Hold from Address Change 000ns

ACE

CE LOW to Data Valid

[13]

15 25 30 ns

DOE

OE LOW to Data Valid

[13]

10 15 20 ns

LZOE

OE LOW to Low Z

[10, 14, 15]

333ns

HZOE

OE HIGH to High Z

[10, 14, 15]

10 15 15 ns

LZCE

CE LOW to Low Z

[10, 14, 15]

355ns

HZCE

CE HIGH to High Z

[10, 14, 15]

10 15 15 ns

CE LOW to Power Up

[10]

000ns

CE HIGH to Power Down

[10]

15 25 25 ns

Write Cycle

[16]

Write Cycle Time 15 25 30 ns

SCE

CE LOW to Write End 12 20 25 ns

Address Setup to Write End 12 20 25 ns

Address Hold from Write End 222ns

Address Setup to Write Start 000ns

PWE

R/WPulse Width 12 15 25 ns

Data Setup to Write End 10 15 15 ns

Data Hold from Write End 000ns

HZWE

R/WLOW to High Z

[15]

10 15 15 ns

LZWE

R/WHIGH to Low Z

[15]

000ns

Shaded areas contain preliminary information.

Notes

12.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified

OH,

and 30 pF load capacitance.

13.AC Test Conditions use V

= 1.6V and V

= 1.4V.

14.At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

15.t

LZCE

, t

LZWE

, t

HZOE

, t

LZOE

, t

HZCE

and t

HZWE

are tested with C

= 5 pF as in part(b) of AC Test Loads.Transition is measured ±500 mV from steady state voltage.

16.The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can

terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 7 of 19

Busy/Interrupt Timing

BLA

BUSY LOW from Address Match 15 20 20 ns

BHA

BUSY HIGH from Address Mismatch

[17]

15 20 20 ns

BLC

BUSY LOW from CE LOW 15 20 20 ns

BHC

BUSY HIGH from CE HIGH

[17]

15 20 20 ns

Port Set Up for Priority 555ns

WB[18]

R/WLOW after BUSY LOW 000ns

R/WHIGH after BUSY HIGH 13 20 30 ns

BDD

BUSY HIGH to Valid Data 15 25 30 ns

DDD

Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns

WDD

Write Pulse to Data Delay Note 19 Note 19 Note 19 ns

Interrupt Timing

WINS

R/Wto INTERRUPT Set Time 15 25 25 ns

EINS

CE to INTERRUPT Set Time 15 25 25 ns

INS

Address to INTERRUPT Set Time 15 25 25 ns

OINR

OE to INTERRUPT Reset Time

[17]

15 25 25 ns

EINR

CE to INTERRUPT Reset Time

[17]

15 25 25 ns

INR

Address to INTERRUPT Reset Time

[17]

15 25 25 ns

Shaded areas contain preliminary information.

Switching Characteristics

Over the Operating Range

[7, 12]

(continued)

Parameter Description

7C131-15

[4]

7C131A-15

7C141-15

7C130-25

[4]

7C131-25

7C140-25

7C141-25

7C130-30

7C130A-30

7C131-30

7C140-30

7C141-30 Unit

Min Max Min Max Min Max

Notes

17.These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.

18.CY7C140/CY7C141 only.

19.A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes HIGH.

Port B’s address is toggled.

CE for Port B is toggled.

R/W for Port B is toggled during valid read.

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 8 of 19

Switching Characteristics

Over the Operating Range

[7,12]

Parameter Description

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45

7C131-45

7C140-45

7C141-45

7C130-55

7C131-55

7C140-55

7C141-55 Unit

Min Max Min Max Min Max

Read Cycle

Read Cycle Time 35 45 55 ns

Address to Data Valid

[13]

35 45 55 ns

OHA

Data Hold from Address Change 0 0 0 ns

ACE

CE LOW to Data Valid

[13]

35 45 55 ns

DOE

OE LOW to Data Valid

[13]

20 25 25 ns

LZOE

OE LOW to Low Z

[10, 14, 15]

333ns

HZOE

OE HIGH to High Z

[10, 14, 15]

20 20 25 ns

LZCE

CE LOW to Low Z

[10, 14, 15]

555ns

HZCE

CE HIGH to High Z

[10, 14, 15]

20 20 25 ns

CE LOW to Power Up

[10]

000ns

CE HIGH to Power Down

[10]

35 35 35 ns

Write Cycle

[16]

Write Cycle Time 35 45 55 ns

SCE

CE LOW to Write End 30 35 40 ns

Address Setup to Write End 30 35 40 ns

Address Hold from Write End 2 2 2 ns

Address Setup to Write Start 0 0 0 ns

PWE

R/WPulse Width 25 30 30 ns

Data Setup to Write End 15 20 20 ns

Data Hold from Write End 0 0 0 ns

HZWE

R/WLOW to High Z

[15]

20 20 25 ns

LZWE

R/WHIGH to Low Z

[15]

000ns

Busy/Interrupt Timing

BLA

BUSY LOW from Address Match 20 25 30 ns

BHA

BUSY HIGH from Address Mismatch

[17]

20 25 30 ns

BLC

BUSY LOW from CE LOW 20 25 30 ns

BHC

BUSY HIGH from CE HIGH

[17]

20 25 30 ns

Port Set Up for Priority 5 5 5 ns

WB[18]

R/W LOW after BUSY LOW 0 0 0 ns

R/W HIGH after BUSY HIGH 30 35 35 ns

BDD

BUSY HIGH to Valid Data 35 45 45 ns

DDD

Write Data Valid to Read Data Valid Note 19 Note 19 Note19 ns

WDD

Write Pulse to Data Delay Note 19 Note19 Note19 ns

Interrupt Timing

WINS

R/Wto INTERRUPT SetTime 25 35 45 ns

EINS

CE to INTERRUPT Set Time 25 35 45 ns

INS

Address to INTERRUPTSetTime 25 35 45 ns

OINR

OE to INTERRUPT Reset Time

[17]

25 35 45 ns

EINR

CE to INTERRUPT Reset Time

[17]

25 35 45 ns

INR

Address to INTERRUPTReset Time

[17]

25 35 45 ns

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 9 of 19

Switching Waveforms

Figure 5. Read Cycle No. 1

[20, 21]

Figure 6. Read Cycle No. 2

[20, 22]

Figure 7. Read Cycle No. 3

[21]

Notes

20.R/W is HIGH for read cycle.

21.Device is continuously selected, CE= V

and OE =

22.Address valid prior to or coincident with CEtransition LOW.

OHA

DATA VALIDPREVIOUS DATAVALID

DATA OUT

ADDRESS

Either Port Address Access

ACE

LZOE

DOE

HZOE

HZCE

DATA VALID

DATA OUT

LZCE

Either Port CE/OE Access

BHA

BDD

VALID

DDD

WDD

ADDRESS MATCH

R/W

ADDRESS

INR

ADDRESS

BUSY

DOUT

BLA

Read with BUSY, Master: CY7C130 and CY7C131

PWE

VALID

[+] Feedback

CY7C130, CY7C130A

CY7C131, CY7C131A

CY7C140, CY7C141

Document #: 38-06002 Rev. *E Page 10of 19

Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port

[16, 23]

Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)

[17, 24]

Switching Waveforms

(continued)

DATA VALID

HIGH IMPEDANCE

SCE

PWE

R/W

ADDRESS

HZOE

OUT

DATA

Either Port

SCE

PWE

HZWE

HIGH IMPEDANCE

DATAVALID

LZWE

ADDRESS

R/W

DATA

OUT

DATA

Notes

23.IfOEis LOW during a R/W controlled write cycle, the writepulsewidthmust be the larger of t

PWE

or t

HZWE

toallowthe dataI/O pins toenterhighimpedance

and for data to be placed on the bus for the required t

24.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.

[+] Feedback

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