Cypress CapSense CY8CMBR2010 Leitfaden

AN75999

CY8CMBR2010 CapSense®Design Guide

Doc. No. 001-75999 Rev. *E

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

http://www.cypress.com

Copyrights

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 2

its subsidiaries, including Spansion LLC (―Cypress‖). This document, including any software or firmware included or

referenced in this document (―Software‖), is owned by Cypress under the intellectual property laws and treaties of the United

States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as

specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property

rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with

Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable

license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code

form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your

organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through

resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents

that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software

solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the

Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR

IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING,

BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without

further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in

this document. Any information provided in this document, including any sample design information or programming code, is

provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test

the functionality and safety of any application made of this information and any resulting product. Cypress products are not

designed, intended, or authorized for use as critical components in systems designed or intended for the operation of

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(including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other

uses where the failure of the device or system could cause personal injury, death, or property damage (―Unintended Uses‖). A

critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the

failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall

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liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-

RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more

complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their

respective owners.

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 3

Contents

1. Introduction....................................................................................................................................................................5

1.1 Abstract .................................................................................................................................................................5

1.2 Cypress’s CapSense Documentation Ecosystem..................................................................................................5

1.3 CY8CMBR2010 CapSense®Express Device Features.........................................................................................7

1.4 Document Conventions .........................................................................................................................................8

2. CapSense Technology..................................................................................................................................................9

2.1 CapSense Fundamentals......................................................................................................................................9

2.2 Capacitive Sensing Method.................................................................................................................................11

2.2.1 CapSense Sigma-Delta (CSD) ...............................................................................................................11

2.3 SmartSense Auto-Tuning ....................................................................................................................................12

2.3.1 Process Variation....................................................................................................................................12

2.3.2 Reduced Design Cycle Time ..................................................................................................................12

3. CapSense Schematic Design .....................................................................................................................................13

3.1 CY8CMBR2010 CapSense Controller Pins.........................................................................................................13

3.1.1 CapSense Buttons (CSx Pins)................................................................................................................13

3.1.2 General Purpose Outputs (GPOx Pins)..................................................................................................13

3.1.3 Modulation Capacitor (CMOD Pin) .........................................................................................................13

3.1.4 Button Auto Reset (ARST/EMC Pin).......................................................................................................14

3.1.5 Noise Immunity (ARST/EMC Pin)...........................................................................................................14

3.1.6 Toggle ON/OFF (Toggle/FSS Pin)..........................................................................................................14

3.1.7 Flanking Sensor Suppression (Toggle/FSS Pin).....................................................................................15

3.1.8 LED ON Time (Delay Pin).......................................................................................................................15

3.1.9 Power-On LED Effects (LEDFading Pin) ................................................................................................16

3.1.10 Analog Voltage Support (LEDFading Pin)...............................................................................................18

3.1.11 Backlighting (Backlighting Pin)................................................................................................................19

3.1.12 CS0 Sensitivity (CS0Sensitivity Pin).......................................................................................................19

3.1.13 CS0 Debounce (CS0Sensitivity Pin).......................................................................................................20

3.1.14 System Diagnostics ................................................................................................................................20

3.1.15 Button Scan Rate (ScanRate/Sleep Pin) ................................................................................................22

3.1.16 Sleep Modes (ScanRate/Sleep Pin) .......................................................................................................23

3.1.17 Serial Debug Data Out (Delay Pin).........................................................................................................23

3.2 Design Toolbox....................................................................................................................................................28

3.2.1 General Layout Guidelines .....................................................................................................................28

3.2.2 Layout Estimator.....................................................................................................................................29

3.2.3 CP, Power Consumption, and Response Time Calculator ......................................................................30

3.2.4 Design Validation....................................................................................................................................31

Contents

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 4

4. Electrical and Mechanical Design Considerations...................................................................................................33

4.1 Overlay Selection.................................................................................................................................................33

4.1.1 Bonding Overlay to PCB.........................................................................................................................34

4.2 ESD Protection....................................................................................................................................................34

4.2.1 Prevent ...................................................................................................................................................34

4.2.2 Redirect ..................................................................................................................................................34

4.2.3 Clamp .....................................................................................................................................................34

4.3 Electromagnetic Compatibility (EMC) Considerations .........................................................................................35

4.3.1 Radiated Interference .............................................................................................................................35

4.3.2 Conducted Immunity and Emissions.......................................................................................................35

4.4 PCB Layout Guidelines........................................................................................................................................35

5. Low-Power Design Considerations............................................................................................................................36

5.1 System Design Recommendations......................................................................................................................36

5.2 Calculating Average Power .................................................................................................................................36

5.2.1 Button Scan Rate (TR) ............................................................................................................................36

5.2.2 Scan Time (TS) .......................................................................................................................................37

5.2.3 Average Current in NO TOUCH State (IAVE_NT).......................................................................................38

5.2.4 Average Current in TOUCH State (IAVE_T)...............................................................................................38

5.2.5 Average Use Current (IAVE_U)..................................................................................................................38

5.2.6 Average Current (IAVE) ............................................................................................................................38

5.2.7 Average Power (PAVE).............................................................................................................................39

5.2.8 Example Calculation...............................................................................................................................39

5.3 Sleep Modes........................................................................................................................................................40

5.3.1 Low-Power Sleep Mode..........................................................................................................................40

5.3.2 Deep Sleep Mode...................................................................................................................................40

6. Resources ....................................................................................................................................................................41

6.1 Website................................................................................................................................................................41

6.2 Datasheet............................................................................................................................................................41

6.3 Design Toolbox....................................................................................................................................................41

6.4 Design Support....................................................................................................................................................41

A. Appendix ......................................................................................................................................................................42

A.1 Schematic Example.............................................................................................................................................42

A.1.1 Schematic 1: Ten Buttons and Ten GPOs..............................................................................................42

A.1.2 Schematic 2: Eight Buttons and Eight GPOs..........................................................................................44

A.2 Acronyms.............................................................................................................................................................45

Glossary................................................................................................................................................................................46

Revision History...................................................................................................................................................................51

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 5

1. Introduction

1.1 Abstract

This document describes how to implement capacitive sensing functionality using Cypress’s CapSense®Express™

CY8CMBR2010 device. The following topics are covered in this guide:

Features of the CY8CMBR2010

CapSense principles of operation

Configuration options of the CY8CMBR2010 device

Using the Design Toolbox with the CY8CMBR2010

System electrical and mechanical design considerations for the CY8CMBR2010

Low-power design considerations for the CY8CMBR2010

Additional resources and support for designing CapSense into your system

1.2 Cypress’s CapSense Documentation Ecosystem

Figure 1-1 and Table 1-1 summarize the CapSense documentation ecosystem. These resources allow the implementers to

quickly access the information needed to complete a CapSense product design. Figure 1-1 shows a typical product design

cycle with capacitive sensing; this document covers the topics highlighted in green. Table 1-1 offers links to the supporting

documents for each of the numbered tasks in Figure 1-1.

Introduction

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 6

Figure 1-1. Typical CapSense Product Design Flow

Introduction

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 7

Table 1-1. Cypress Documents Supporting Numbered Design Tasks of Figure 1-1

Numbered Design Task of

Figure 1-1

Supporting Cypress CapSense Documentation

Getting Started with CapSense

CY8CMBR2010 Device Datasheet

Getting Started with CapSense

This document

Not applicable for CY8CMBR2010

This document

1.3 CY8CMBR2010 CapSense®Express Device Features

Cypress’s low-power CapSense controller can easily add capacitive touch sensing to your user interface. The device’s

features include:

Hardware Configurable CapSense Controller

Does not require software tools or programming

Ten button solution configurable through hardware straps

Ten general-purpose outputs (GPOs)

GPOs are linked to CapSense buttons

GPOs support direct LED drive

SmartSense™ Auto-Tuning

Maintains optimal button performance even in noisy environment

CapSense parameters dynamically set in runtime

Saves time and effort in device tuning

Wide parasitic capacitance (CP) range (5—40 pF)

Advanced Features

Robust sensing with closely spaced buttons –Flanking Sensor Suppression (FSS)

User-configurable LED Effects

oOn-system power-on

oLED ON Time after button release

Analog voltage output

oUsing external resistor bridge

Serial debug data output

oSimplifies production-line testing and system debug

Introduction

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 8

Noise Immunity

Specifically designed for superior noise immunity to external radiated and conducted noise

Low radiated noise emission

System Diagnostics

Button shorts

Improper value of modulating capacitor (CMOD)

Parasitic capacitance (CP) value out of range

Wide operating voltage range

1.71—5.5 V

Ideal for both regulated and unregulated battery applications

Low power consumption

Average current consumption of 21 µA[1] per button

Deep sleep current: 100 nA

Industrial temperature range: –40 °C to +85 °C.

32-pin QFN package (5 mm x 5 mm x 0.6 mm)

1.4 Document Conventions

Convention

Usage

Courier New

Displays file locations, user entered text, and source code:

C:\ ...cd\icc\

Italics

Displays file names and reference documentation:

Read about the sourcefile.hex file in the PSoC Designer User Guide.

[Bracketed, Bold]

Displays keyboard commands in procedures:

[Enter] or [Ctrl] [C]

File > Open

Represents menu paths:

File > Open > New Project

Bold

Displays commands, menu paths, and icon names in procedures:

Click the File icon and then click Open.

Times New Roman

Displays an equation:

2 + 2 = 4

Text in gray boxes

Describes Cautions or unique functionality of the product.

1Four buttons used, 3% touch time, 10 pF < (Cp of all buttons) < 20 pF, Button Scan Rate = 556 ms, power consumption optimized, Noise

Immunity level "Normal", CS0 sensitivity "High"

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 9

2. CapSense Technology

2.1 CapSense Fundamentals

CapSense is a touch sensing technology that works by measuring the capacitance of each sensor input pin on the CapSense

controller. The total capacitance on each of the sensor pins can be modeled as equivalent lumped capacitors with values of

CX,1 through CX,n as shown in Figure 2-1. Circuitry internal to the CY8CMBR2010 device converts the magnitude of each CX

into a digital code that is stored for post-processing. A modulating capacitor, CMOD, is used by the CapSense controller’s

internal circuitry. CMOD is discussed in more detail in Capacitive Sensing Method.

Figure 2-1. CapSense Implementation in a CY8CMBR2010 Device

Each sensor input pin is connected to a sensor pad by traces, vias, or both, as necessary. A nonconductive overlay is required

to cover the sensor pad and constitutes the product’s touch interface. When a finger comes into contact with the overlay, the

conductivity and mass of the body effectively introduces a grounded conductive plane parallel to the sensor pad. This action is

represented in Figure 2-2. This arrangement constitutes a parallel plate capacitor, whose capacitance is given by Equation 1:

=0

Equation 1

Where:

CF= The capacitance affected by a finger in contact with the overlay over a sensor

ε0= Free space permittivity

εr= Dielectric constant (relative permittivity) of overlay

A = Area of finger and sensor pad overlap

D = Overlay thickness

CMBR

2010

MOD

Sensor

Capacitors

CapSense Technology

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 10

Figure 2-2. Section of Typical CapSense PCB with the Sensor Being Activated by a Finger

In addition to the parallel plate capacitance, a finger in contact with the overlay causes electric field fringing between itself and

other conductors in the immediate vicinity. Typically, the effect of these fringing fields is minor, and it can usually be ignored.

Even without a finger touching the overlay, the sensor input pin has some parasitic capacitance (CP). CPresults from the

combination of the CapSense controller internal parasitic and electric field coupling among the sensor pad, traces, and vias,

and other conductors in the system, such as ground plane, other traces, any metal in the product’s chassis or enclosure, and

so on. The CapSense controller measures the total capacitance (CX) connected to a sensor pin.

When a finger is not touching a sensor:

= Equation 2

With a finger on the sensor, CXequals the sum of CPand CF:

=+Equation 3

In general, CPis an order of magnitude greater than CF. CPusually ranges from 10—20 pF, but in extreme cases it can be as

high as 40 pF. CFusually ranges from 0.1—0.4 pF.

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