Cypress Traveo S6J3310 Series Bedienungsanleitung

S6J3310 Series

S6J3320 Series

S6J3330 Series

S6J3340 Series

32-bit Microcontroller

Traveo™ Family

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 002-10635 Rev. *I Revised September 5, 2018

The Traveo family expands the company’s automotive applications, scalability and high performance into one line-up and at the

same time adds new features to fulfill the latest requirements of the automotive industry. Based on the powerful Arm® Cortex®- R5F

core in single operations, it offers state-of-the-art real time performance, safety and security features. The family supports the latest

in-car networks and offers high performance graphics engines optimized for a minimum memory footprint and embeds dedicated

features to increase data security in the car.

S6J3310/20/30/40 is a microcontroller series for instrument clusters with small thin-film transistor (TFT) displays.

Features

System

32-bit Arm Cortex-R5F CPU core at up to 240 MHz

General purpose I/O port: up to 148

12-bit A/D converter: up to 48 channels

External interrupt: up to 24 channels

Base timer: up to 32 channels

32-bit reload timer: up to 6 channels

32-bit free-run timer: 8 channels

Input capture unit: 12 channels

Output compare unit: 12 channels

Stepper motor controller (SMC): 6 Units

Built-in CR oscillator

Real-time clock

DMA controller: 16 channels

JTAG debug interface

Graphics and Display (optional)

2D graphic engine

RGB888

LCD：up to 4 COM x 32 SEG

Communication

CAN-FD: up to 6 channels

Multi-function serial interface: up to 12 channels,

selectable protocol: UART, CSIO, LIN and I2C

Ethernet AVB MAC (optional)

MediaLB (optional)

Automotive Remote Handler for APIX® (optional)

Memory

HyperBus™ Memory interface

DDR High Speed SPI

External BUS interface

Multimedia (optional)

I2S input/output: 2 channels

PCM to PWM output unit

Sound mixer: 1 unit x 10 inputs

Stereo audio DAC

Security and Safety

Secure Hardware Extension – SHE

Safety features, such as MPU, TPU, ECC and others

CRC generator: 1 channel

Watchdog timer with window function

Low voltage detector

Clock supervisor for all source clocks

Applications

Instrument cluster

 
 
 
 
 
Document Number: 002-10635 Rev. *I Page 2 of 325 
 
 
 
S6J3310/20/30/40 Series 
 
Table of Contents 
Overview........................................................................3 
1 Overview ...................................................................3 
2 Document Definition..................................................3 
Function List .................................................................4 
1 Function List..............................................................4 
2 Optional Function......................................................6 
Product Description......................................................9 
1 Overview ...................................................................9 
2 Product Description...................................................9 
Package and Pin Assignment....................................15 
1 Pin Assignment .......................................................15 
2 Package Dimensions...............................................27 
IO Circuit Type ............................................................31 
1 I/O Circuit Type .......................................................31 
2 Note.........................................................................36 
Port Description..........................................................37 
1 Port Description List ................................................37 
2 Remark................................................................... 58 
Port Configuration...................................................... 59 
1 Resource Input Configuration Module .................... 59 
2 Port Output Function Configuration ...................... 148 
Precautions and Handling Devices......................... 158 
1 Handling Precautions............................................ 158 
2 Handling Devices.................................................. 161 
Electric Characteristics............................................ 163 
1 Electrical Characteristics....................................... 163 
Acronyms.................................................................. 261 
Ordering Information................................................ 262 
Errata......................................................................... 263 
Appendix................................................................... 265 
1 Application 1: JTAG Tool Connection................... 265 
Major Changes.......................................................... 266 
Document History.......................................................... 323 
Sales, Solutions, and Legal Information...................... 325 
 

Document Number: 002-10635 Rev. *I Page 3 of 325

S6J3310/20/30/40 Series

1. Overview

1.1 Overview

S6J3310/20/30/40 is a microcontroller series which is to be applied to automotive systems representative of a graphical cluster

control unit on a dashboard.

1.2 Document Definition

The related documents of S6J3310/20/30/40 are the followings.

Table 1-1: Document Definition

Document Type

Definition

Primary User

Document Code

S6J3310/20/30/40

Datasheet

This document.

The function and its characteristics

are specified quantitatively.

Investigator and hardware

engineer

002-10635

S6J3300 Hardware

Manual

S6J3300 Series 32-bit Microcontroller

Traveo™ Family Hardware Manual

The function and its operation of

S6J3300 series are described.

Software engineer

002-10185

TraveoTM Platform

Hardware Manual

32-Bit Microcontroller Traveo™

Family S6J33xx, S6J34xx, S6J35xx

Series Hardware Manual Platform

Part

The function and its operation of CPU

core platform are described.

Software engineer

002-07884

Application Note

The reference software, sample

application, the reference board

design and so on are explained.

Software and hardware engineer

002-03898

002-04455

002-04446

002-09716

002-04452

002-04096

002-12061

002-02495

Notes:

−Refer all documents for the system development.

−"Primary user" is a most likely engineer for whom the document is the most useful.

−The description of the datasheet and the S6J3300 Hardware Manual should precede the duplicated description of TraveoTM

Platform Hardware Manual.

−TraveoTM Platform Hardware Manual is expected to be used as dictionary of platform specification.

Document Number: 002-10635 Rev. *I Page 4 of 325

S6J3310/20/30/40 Series

2. Function List

2.1 Function List

The table shows the functions which are implemented in S6J3310/20/30/40 series.

Table 2-1: Function List

Function

S6J3310

S6J3320

S6J3330

S6J3340

Remarks

CPU core

Arm Cortex R5F

FPU

Available

PPU

Available

MPU

Available

TPU

Available

Endian

Little endian

Core clock frequency

240 MHz

HPM bus frequency

200 MHz

LLPM bus frequency

240 MHz

Resource clock frequency

80 MHz (Max)

Embedded CR oscillation

Slow clock:100 kHz,

Fast clock: 4 MHz

(Center frequency)

See 9.1.4.1

PLL

PLL0, 1, 2, 3

SSCG PLL

SSCG0, 1, 2, 3

Clock supervisor

Available

DMA

16 ch

Boot-ROM

16 Kbyte

JTAG

Available

Data cache

16 Kbyte

Instruction cache

16 Kbyte

Program FLASH

Option

See 2.2.1

Work FLASH

112 Kbyte

TCRAM

128 Kbyte

System SRAM

384 Kbyte

Backup RAM

32 Kbyte

Security (SHE)

Option

Low latency interrupt

Available

Power domain

5 domains

External power supply

5 V (VCC5, VCC53),

3 V (VCC3, VCC53),

1.2 V (VCC12)

Embedded LDO power supply

for 5.0 V

Available

Low voltage detection of

external power supply

Available

Low voltage detection of

internal LDO output

Available

Hardware watchdog timer

Available

Software watchdog timer

Available

Package

Option

See 2.2.1

AUTOSAR

AUTOSAR 4.0.3

General Purpose I/O

Option

See 2.2.3

Up/down counter

2 ch

I/O timer

(FRT 5 ch x ICU 6 ch x OCU 6 ch) + (FRT 3 ch x ICU 6 ch x OCU 6

ch)

32bit Reload timer

6 ch

Real time clock

Available

Automatic calibration

Sound generator

5 ch

Sound waveform generator

1 unit x 5 outputs

See 2.2.1

Sound mixer

1 unit x 10 inputs

See 2.2.1

Document Number: 002-10635 Rev. *I Page 5 of 325

S6J3310/20/30/40 Series

Function

S6J3310

S6J3320

S6J3330

S6J3340

Remarks

Stereo audio DAC

1 unit (L and R)

See 2.2.1

PCM-PWM

1 unit (L and R)

See 2.2.1

Base timer

16 units (32 ch)

Stepping motor controller

(SMC)

For 6 gauges

12bit-A/D converter

2 unit - 48 input ports (Max)

See 2.2.3

CRC

4 units

Programmable CRC

1 unit

Source clock timer

4 ch

NMI

Available

External interrupt

24 ch

Internal interrupt

512 vectors

I2S

2 ch

1 ch

One only supports

an output as a

function of the sound

system.

DDR HSSPI

1 ch

A type of Quad SPI

Hyper BUS

1 ch

See the AC

specification on

9.1.4.17.

Multi-function serial interface

12 ch

CAN-FD

6 ch

CAN-FD RAM (ECC

supported)

16 KB/ch

It equivalents to 128 message buffer per channel of MCAN module

Ethernet AVB

1 unit

See 2.2.1

Media-LB (MOST50)

1 unit

See 2.2.1

LCD controller

4 COM x 32 SEG (Max)

See 2.2.3

Indicator PWM

1 ch

MPU for AHB

1 unit

MPU for AXI

1 unit

Graphic engine clock

80 MHz (Max)

Graphic AXI clock

80 MHz (Max)

Display clock

25 MHz

Display clock source

Graphic display controller clock or external clock

Target resolution

WQVGA 480 x 272

Target frame rate

60 fps

Number of display outputs

1 output

TTL output (RGB888)

Option

See 2.2.1

2D Graphic engine

1 unit

2D Driver API

CYPRESS proprietary

External BUS

1 ch

APIX® for ARH

(Automotive Remote Handler)

1 unit (2 ch)

See 2.2.1

Notes:

−The options are described in 2.2.

Document Number: 002-10635 Rev. *I Page 6 of 325

S6J3310/20/30/40 Series

2.2 Optional Function

2.2.1 Basic Option

The figure shows the optional function and the part number relations of the series.

Figure 2-1: Option and Part Number for S6J3310/20/30/40 Series

Notes:

−This table only shows the relations between the optional function and the part numbers. That is, all products are not

necessarily available for orders. See 11, and confirm actual availabilities of products.

−The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0.

S 6 J 3 x x x x x x x

Digit

Digit SHE MK_CEER* VCC DVCC

S5V

B3V

U5V

D3V

T5V

F3V

V5V

H3V

Digit Pin Count

H144pin

J176pin

K208pin

Program Work Main Backup

E4,160KB 112KB 512KB 16+16KB

D3,136KB 112KB 512KB 16+16KB

C2,112KB 112KB 512KB 16+16KB

B1,600KB 112KB 512KB 16+16KB

Digit Graphic Ethernet MediaLB

Sound

System

ARH for

APIX

1Yes Yes Yes Yes Yes

2Yes Yes Yes Yes -

3Yes Yes Yes - -

4Yes - - - -

Selectable

OFF

Identifer: Automotive MCU

* Chip Erase Enable Register

Pin count:

Memory size:

Digit

Flash

RAM

Function:

Product series

Revision:

Option:

Fixed to

Enable

Fixed TCFLASH Sector Write Permission and Data Retention after Reset

OFF

Fixed Stabilization time for sub oscillator

Leakage current improvement

Fixed Operation frequency of embedded Program Flash and CPU,

Description

Ordering options 7 digit

Document Number: 002-10635 Rev. *I Page 7 of 325

S6J3310/20/30/40 Series

2.2.2 ID

ID is specified for each function digit and revision which is defined at Figure 2-1.

Function Digit

Revision

Chip ID

JTAG ID

S,U,T,V

0x10122100

0x1000B5CF

D, E

0x10122200

A,C,E,G

0x10128100

D, E

0x10128200

B,D,F,H

0x10120100

D, E

0x10120200

2.2.3 Restriction

Some functions have restrictions which depend on package pin counts.

Table 2-2: Pin Restriction

Function

TEQFP176

TEQFP144

Analog input port (12bit-

ADC)

AN4~7, AN10~11,

AN14~15,

AN25~26, AN28~30,

SEG port of LCD controller

SEG0~3

SEG5~8

General Purpose I/O

P4_00 ~ P4_31

P3_00 ~ P3_31

CAN

RX0_2, TX0_2

RX1_0, TX1_0

RX1_1, TX1_1

RX2_0, TX2_0

RX2_1, TX2_1

RX3_2, TX3_2

RX0_1, TX0_1

RX0_2, TX0_2

RX1_0, TX1_0

RX1_1, TX1_1

RX2_0, TX2_0

RX2_1, TX2_1

RX3_1, TX3_1

RX3_2, TX3_2

RX5_1, TX5_1

RX6_1, TX6_1

BaseTimer

PPG4/5/6/7/8/9_TOUT0_1

PPG4/5/6/7/8/9_TOUT2_1

PPG10/11/12/13/15_TOUT0_1

PPG10/11/12/13/14/15_TOUT2_1

PPG0/1/2/3/4/5_TIN1_1

PPG6/7/8/9/10/11_TIN1_1

PPG12/13/14/15_TIN1_1

ExtBus

MDQM1

MAD15~21

MDATA8~15

Document Number: 002-10635 Rev. *I Page 8 of 325

S6J3310/20/30/40 Series

Function

TEQFP176

TEQFP144

External Interrupt

EINT1_4, EINT1_5

EINT2_1, EINT2_2

EINT3_2, EINT4_2

EINT5_4, EINT5_5

EINT6_4, EINT7_1

EINT7_4, EINT8_4

EINT8_5, EINT9_1

EINT10_1, EINT10_4

EINT10_5, EINT13_2

EINT13_3, EINT14_2

EINT14_3, EINT15_3

EINT16_1, EINT16_3

EINT16_4, EINT19_4

EINT20_3, EINT21_3

EINT22_1, EINT22_3

EINT23_3, EINT23_4

EINT0_4, EINT1_1

EINT1_4, EINT1_5

EINT2_1, EINT2_2

EINT2_4, EINT3_1

EINT3_2, EINT3_4

EINT4_2, EINT4_4

EINT5_4, EINT5_5

EINT6_1, EINT6_4

EINT7_1, EINT7_4

EINT8_1, EINT8_4

EINT8_5, EINT9_1

EINT9_2, EINT10_1

EINT10_2, EINT10_4

EINT10_5, EINT11_2

EINT11_5, EINT12_1

EINT12_2, EINT12_5

EINT13_2, EINT13_3

EINT13_5, EINT14_1

EINT14_2, EINT14_3

EINT14_5, EINT15_2

EINT15_3, EINT16_1

EINT16_2, EINT16_3

EINT16_4, EINT16_5

EINT17_1, EINT17_3

EINT17_5, EINT18_1

EINT18_3, EINT18_5

EINT19_1, EINT19_3

EINT19_4, EINT20_1

EINT20_2, EINT20_3

EINT21_1, EINT21_3

EINT22_1, EINT22_3

EINT23_3, EINT23_4

Notes:

−See multiplexed functions on pin assignment sheet.

−The optional restriction will be added without notification.

Document Number: 002-10635 Rev. *I Page 9 of 325

S6J3310/20/30/40 Series

3. Product Description

3.1 Overview

This chapter explains the product features of S6J3310/20/30/40 series. The description of this chapter should precede the

duplicated description on TraveoTM Platform Hardware Manual.

3.2 Product Description

The table shows features.

Table 3-1: Product Features

Feature

Description

Technology

40-nm CMOS technology with embedded FLASH

Fully automotive qualified according to ISO/TS 16949 and AEC-Q100

Developed according to ISO26262, safety target ASIL-B

Functional Safety

The product series has some functional safety features suited for ASIL-B application.

Peripherals

See function list.

Power Domain (PD)

See the TraveoTM Platform Hardware Manual and chapter STATE TRANSITION in detail.

The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0,

PD4_1 and PD6.

The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series,

and "0" is always read from the reset factor flags of them.

This series doesn't support partial wakeup for PD6.

Debug and Trace

See the TraveoTM Platform Hardware Manual in detail.

−Standard 5-pin JTAG interface

−4 kB Embedded Trace Buffer

4-bit trace support for TEQFP package.

System Control

See the TraveoTM Platform Hardware Manual in detail.

Main and sub oscillator is available.

−A wide range of 3.6 - 16MHz is available for main oscillator

−32KHz is available for sub oscillator

Sub clock is enable/disable by register settings

Clock

See the TraveoTM Platform Hardware Manual in detail.

CLK_CLKO (Clock Output Function) is supported.

Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value)

Embedded CR oscillation

See the TraveoTM Platform Hardware Manual in detail.

Stabilization time is as followings.

−0.35 ms to 0.8 ms for 4 MHz (Fast clock)

−0.43 ms to 1.28 ms for 100 kHz (Slow clock)

Clock Supervisor

See the TraveoTM Platform Hardware Manual in detail.

This product series doesn’t support clock supervisor output port. (Related register and internal

circuit is implemented.)

Reset

RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input)

−Occurrence factor: Simultaneously inputting “L” level to RSTX pin and inputting “L” level to MD

−Release factor: Inputting “H” level to RSTX pin

See the TraveoTM Platform Hardware Manual in detail.

Following resets are not mounted on this device.

−SRSTX (and nSRST pin)

The product series does not support EX5VRST and writing EX5VRSTCNT bits in

SYSC0_SPECFGR has no effect.

Document Number: 002-10635 Rev. *I Page 10 of 325

S6J3310/20/30/40 Series

Feature

Description

Hardware watchdog

See the TraveoTM Platform Hardware Manual in detail.

Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the

bit

ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK = 1).

The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and

internal circuit is implemented.)

Standby mode

See the TraveoTM Platform Hardware Manual in detail.

Standby mode with 5 V (or 3 V) single external power supply is available.

Turning off the 1.2 V external power supply in standby mode is available.

The long term pulse of the indicator PWM can be outputted during RTC Standby mode.

PLL / SSCG PLL

See the TraveoTM Platform Hardware Manual in detail.

Use case assumption is following.

PLL

−Sound system clock

−Sound frequency master clock

−Peripherals

−Display clock

−Trace clock

SSCG

−CPU core

−GDC core

−Hyper BUS

−DDR-HSSPI

Product supports down spread and center spread modes with the conditions defined in 9.1.4.3

Internal Clock Timing (S6J3310).

External Interrupts

See the TraveoTM Platform Hardware Manual in detail.

NMI

See the TraveoTM Platform Hardware Manual in detail.

1 NMI pin.

Memory Protection

MPU16 AHB: See the TraveoTM Platform Hardware Manual in detail.

MPU for AXI: ch.0

MPU for AHB: ch.1

Additional MPU for Graphic sub system, MediaLB and Ethernet AVB. They are described on the

chapter of MPU for AHB and MPU for AXI

To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,

− Lock: 0x112ABB56

− Unlock: 0xACCABB56

Peripheral Protection

See the TraveoTM Platform Hardware Manual in detail.

Protected peripherals are described in the base address map.

Internal Memories

System SRAM

384 KByte

1 wait cycle is necessary for RAM read at over 120MHz.

Internal Memories

TCRAM

128 KByte

Internal Memories

Backup RAM

32 KByte

Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the

memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM

is not supported and cannot be used.

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