Philips UDA1334BT Bedienungsanleitung

DATA SHEET

Product speciﬁcation 2002 May 22

INTEGRATED CIRCUITS

UDA1334BT

Low power audio DAC

2002 May 22 2

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format data interface

1.3 DAC digital sound processing

1.4 Advanced audio configuration

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 QUICK REFERENCE DATA

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.2 Interpolation filter

8.3 Noise shaper

8.4 Filter stream DAC

8.5 Power-on reset

8.6 Feature settings

8.6.1 Digital interface format select

8.6.2 Mute control

8.6.3 De-emphasis control

8.6.4 Power control and sampling frequency select

9 LIMITING VALUES

10 HANDLING

11 THERMAL CHARACTERISTICS

12 QUALITY SPECIFICATION

13 DC CHARACTERISTICS

14 AC CHARACTERISTICS

14.1 2.0 V supply voltage

14.2 3.0 V supply voltage

14.3 Timing

15 APPLICATION INFORMATION

16 PACKAGE OUTLINE

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

18 DATA SHEET STATUS

19 DEFINITIONS

20 DISCLAIMERS

2002 May 22 3

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

1 FEATURES

1.1 General

•1.8 to 3.6 V power supply voltage

•Integrated digital filter plus DAC

•Supports sample frequencies from 8 to 100 kHz

•Automatic system clock versus sample rate detection

•Low power consumption

•No analog post filtering required for DAC

•Slave mode only applications

•Easy application

•SO16 package.

1.2 Multiple format data interface

•I2S-bus and LSB-justified format compatible

•1fsinput data rate.

1.3 DAC digital sound processing

•Digital de-emphasis for 44.1 kHz sampling rate

•Mute function.

1.4 Advanced audio conﬁguration

•High linearity, wide dynamic range and low distortion

•Standby or Sleep mode in which the DAC is powered

down.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio

portable application, such as portable MD, MP3 and

DVD players.

3 GENERAL DESCRIPTION

The UDA1334BT supports the I2S-bus data format with

word lengths of up to 24 bits and the LSB-justified serial

data format with word lengths of 16, 20 and 24 bits.

The UDA1334BT has basic features such as de-emphasis

(at 44.1 kHz sampling rate) and mute.

4 ORDERING INFORMATION

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

UDA1334BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

2002 May 22 4

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

5 QUICK REFERENCE DATA

Note

1. The DAC output voltage scales proportionally to the power supply voltage.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage 1.8 2.0 3.6 V

VDDD digital supply voltage 1.8 2.0 3.6 V

IDDA DAC analog supply current normal operating mode −2.3 −mA

Sleep mode −125 −µA

DDD digital supply current normal operating mode −1.4 −mA

Sleep mode

clock running −250 −µA

no clock running −20 −µA

amb ambient temperature −40 −+85 °C

Digital-to-analog converter (VDDA =V

DDD = 2.0 V)

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 −600 −mV

(THD + N)/S total harmonic

distortion-plus-noise to signal

ratio

fs= 44.1 kHz; at 0 dB −−80 −dB

fs= 44.1 kHz; at −60 dB; A-weighted −−37 −dB

fs= 96 kHz; at 0 dB −−75 −dB

fs= 96 kHz; at −60 dB; A-weighted −−35 −dB

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0; A-weighted −97 −dB

fs= 96 kHz; code = 0; A-weighted −95 −dB

αcs channel separation −100 −dB

Digital-to-analog converter (VDDA =V

DDD = 3.0 V)

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 −900 −mV

(THD + N)/S total harmonic

distortion-plus-noise to signal

ratio

fs= 44.1 kHz; at 0 dB −−90 −dB

fs= 44.1 kHz; at −60 dB; A-weighted −−40 −dB

fs= 96 kHz; at 0 dB −−85 −dB

fs= 96 kHz; at −60 dB; A-weighted −−37 −dB

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0; A-weighted −100 −dB

fs= 96 kHz; code = 0; A-weighted −98 −dB

αcs channel separation −100 −dB

Power dissipation (at fs= 44.1 kHz)

P power dissipation playback mode

at 2.0 V supply voltage −7.4 −mW

at 3.0 V supply voltage −17 −mW

Sleep mode; at 2.0 V supply voltage

clock running −0.75 −mW

no clock running −0.3 −mW

2002 May 22 5

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

6 BLOCK DIAGRAM

handbook, full pagewidth

MGU676

DAC

UDA1334BT

NOISE SHAPER

INTERPOLATION FILTER

DE-EMPHASIS

DAC

DIGITAL INTERFACE

13 12

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

SFOR0

SYSCLK 8

MUTE 9

DEEM 10

PCS

SFOR1

Fig.1 Block diagram.

2002 May 22 6

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

7 PINNING

Notes

1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages

this is maximum 3.3 V tolerant.

2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a

maximum of 0.5 V above that level.

SYMBOL PIN PAD TYPE DESCRIPTION

BCK 1 5 V tolerant digital input pad; note 1 bit clock input

WS 2 5 V tolerant digital input pad; note 1 word select input

DATAI 3 5 V tolerant digital input pad; note 1 serial data input

VDDD 4 digital supply pad digital supply voltage

VSSD 5 digital ground pad digital ground

SYSCLK 6 5 V tolerant digital input pad; note 1 system clock input

SFOR1 7 5 V tolerant digital input pad; note 1 serial format select 1

MUTE 8 5 V tolerant digital input pad; note 1 mute control

DEEM 9 5 V tolerant digital input pad; note 1 de-emphasis control

PCS 10 3-level input pad; note 2 power control and sampling frequency select

SFOR0 11 digital input pad; note 2 serial format select 0

Vref(DAC) 12 analog pad DAC reference voltage

VDDA 13 analog supply pad DAC analog supply voltage

VOUTL 14 analog output pad DAC output left

VSSA 15 analog ground pad DAC analog ground

VOUTR 16 analog output pad DAC output right

handbook, halfpage

MGU675

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

SFOR0SYSCLK

PCSSFOR1

DEEMMUTE

UDA1334BT

Fig.2 Pin configuration.

2002 May 22 7

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334BT operates in slave mode only; this means

that in all applications the system must provide the system

clock and the digital audio interface signals

(BCK and WS).

Thesystemclockmustbelockedinfrequencytothedigital

interface signals.

The UDA1334BT automatically detects the ratio between

the SYSCLK and WS frequencies.

The BCK clock can be up to 64fs, or in other words the

BCK frequency is 64 times the Word Select (WS)

frequency or less: fBCK ≤64 ×fWS.

Remarks:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O

data interface

2. For LSB-justified formats it is important to have a WS

signal with a duty factor of 50%.

The modes which are supported are given in Table 1.

Table 1 Supported sampling ranges

Notes

1. This mode can only be supported for power supply

voltages down to 2.4 V. For lower voltages, in

192fsmode the sampling frequency should be limited

to 55 kHz.

2. Not supported in the low sampling frequency mode.

An example is given in Table 2 for a 12.228 MHz system

clock input.

Table 2 Example using a 12.228 MHz system clock

Note

1. This mode can only be supported for power supply

voltages down to 2.4 V. For lower voltages, in 192fs

mode the sampling frequency should be limited to

55 kHz.

8.2 Interpolation ﬁlter

The interpolation digital filter interpolates from 1fsto 64fs

by cascading FIR filters (see Table 3).

Table 3 Interpolation ﬁlter characteristics

8.3 Noise shaper

The 5th-order noise shaper operates at 64fs. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using a

Filter Stream DAC (FSDAC).

CLOCK MODE SAMPLING RANGE

768fs8to55kHz

512fs8 to 100 kHz

384fs8 to 100 kHz

256fs8 to 100 kHz

192fs8 to 100 kHz(1)(2)

128fs8 to 100 kHz(2)

CLOCK MODE SAMPLING FREQUENCY

128fs96 kHz

192fs64 kHz(1)

256fs48 kHz

384fs32 kHz

512fs24 kHz

768fs16 kHz

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45fs±0.02

Stop band >0.55fs−50

Dynamic range 0 to 0.45fs>114

2002 May 22 8

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

8.4 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output voltage. The filter coefficients are

implemented as current sources and are summed at

virtual ground of the output operational amplifier. In this

way very high signal-to-noise performance and low clock

jitter sensitivity is achieved. No post-filter is needed due to

the inherent filter function of the DAC. On-board amplifiers

convert the FSDAC output current to an output voltage

signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally

with the power supply voltage.

8.5 Power-on reset

The UDA1334BT has an internal Power-on reset circuit

(see Fig.3) which resets the test control block.

The reset time (see Fig.4) is determined by an external

capacitor which is connected between pin Vref(DAC) and

ground. The reset time should be at least 1 µs for

Vref(DAC) < 1.25 V. When VDDA is switched off, the device

will be reset again for Vref(DAC) < 0.75 V.

During the reset time the system clock should be running.

handbook, halfpage

VDDA

Vref(DAC)

3.0 V 13

MGU678

UDA1334BT

C1 >

10 µF

RESET

CIRCUIT

50 kΩ

Fig.3 Power-on reset circuit.

handbook, halfpage

3.0

VDDD

(V)

1.5

3.0

VDDA

(V)

1.5

3.0

Vref(DAC)

(V)

1.5

1.25

0.75

MGL984

>1 µs

Fig.4 Power-on reset timing.

2002 May 22 9

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

8.6 Feature settings

The features of the UDA1334BT can be set by control

pins SFOR1, SFOR0, MUTE, DEEM and PCS.

8.6.1 DIGITAL INTERFACE FORMAT SELECT

The digital audio interface formats (see Fig.5) can be

selected via the pins SFOR1 and SFOR0 as shown in

Table 4.

Table 4 Data format selection

8.6.2 MUTE CONTROL

The output signal can be soft muted by setting pin MUTE

to HIGH level as shown in Table 5.

Table 5 Mute control

8.6.3 DE-EMPHASIS CONTROL

De-emphasis can be switched on for fs= 44.1 kHz by

setting pin DEEM at HIGH level. The function description

of pin DEEM is given in Table 6.

Table 6 De-emphasis control

Remark: the de-emphasis function in only supported in

the normal operating mode, not in the low sampling

frequency mode.

8.6.4 POWER CONTROL AND SAMPLING FREQUENCY

SELECT

Pin PCS is a 3-level pin and is used to set the mode of the

UDA1334BT. The definition is given in Table 7.

Table 7 PCS function deﬁnition

The low sampling frequency mode is required to have a

higher oversampling rate in the noise shaper in order to

improve the signal-to-noise ratio. In this mode the

oversamplingratioofthenoiseshaperwill be128fsinstead

of 64fs.

SFOR1 SFOR0 INPUT FORMAT

LOW LOW I2S-bus input

LOW HIGH LSB-justiﬁed 16 bits input

HIGH LOW LSB-justiﬁed 20 bits input

HIGH HIGH LSB-justiﬁed 24 bits input

MUTE FUNCTION

LOW mute off

HIGH mute on

DEEM FUNCTION

LOW de-emphasis off

HIGH de-emphasis on

PCS FUNCTION

LOW normal operating mode

MID low sampling frequency mode

HIGH Power-down or Sleep mode

2002 May 22 10

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

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handbook, full pagewidth

MGS752

B5 B6 B7 B8 B9 B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

BCK

DATA

RIGHT

1518 1720 1922 212324 2 1

B3 B4

MSB B2 B23 LSB

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

BCK

DATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

BCK

DATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB MSBB2

21> = 812 3

LEFT

I2S-BUS FORMAT

BCK

DATA

RIGHT

3> = 8

MSB B2

Fig.5 Digital audio formats

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