ST ST10 Series Betriebsanleitung

1/197 Rev 8 September 2013

ST10 FAMILY

PROGRAMMING

MANUAL

PROGRAMMING MANUAL

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Table of Contents

1 Standard Instruction Set - - - - - - - - - - - - - - - - - - - 5

1.1 Addressing modes - - - - - - - - - - - - - - - - - - - - - - - 5

1.1.1 Short adressing modes - - - - - - - - - - - - - - - - - - - - - - - - -5

1.1.2 Long addressing mode - - - - - - - - - - - - - - - - - - - - - - - - - 6

1.1.3 DPP override mechanism - - - - - - - - - - - - - - - - - - - - - - - - 8

1.1.4 Indirect addressing modes - - - - - - - - - - - - - - - - - - - - - - - 9

1.1.5 Constants - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10

1.1.6 Branch target addressing modes - - - - - - - - - - - - - - - - - - - 11

1.2 Instruction execution times - - - - - - - - - - - - - - - - - - 12

1.2.1 Definition of measurement units - - - - - - - - - - - - - - - - - - - - 12

1.2.2 Minimum state times - - - - - - - - - - - - - - - - - - - - - - - - - 14

1.2.3 Additional state times - - - - - - - - - - - - - - - - - - - - - - - - - 15

1.3 Instruction set summary - - - - - - - - - - - - - - - - - - - 17

1.4 Instruction set ordered by functional group - - - - - - - - - - 21

1.5 Instruction set ordered by opcodes - - - - - - - - - - - - - - 37

1.6 Instruction conventions - - - - - - - - - - - - - - - - - - - - 45

1.6.1 Instruction name - - - - - - - - - - - - - - - - - - - - - - - - - - - 46

1.6.2 Syntax - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46

1.6.3 Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46

1.6.4 Data types - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48

1.6.5 Description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48

1.6.6 Condition code - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48

1.6.7 Flags - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50

1.6.8 Addressing modes - - - - - - - - - - - - - - - - - - - - - - - - - - 51

1.7 ATOMIC and EXTended instructions - - - - - - - - - - - - - 53

1.8 Instruction descriptions - - - - - - - - - - - - - - - - - - - - 54

2 MAC Instruction set - - - - - - - - - - - - - - - - - - - - - 139

2.1 Addressing modes - - - - - - - - - - - - - - - - - - - - - - 139

2.2 MAC instruction execution time - - - - - - - - - - - - - - - - 140

2.3 MAC instruction set summary - - - - - - - - - - - - - - - - - 141

2.4 MAC instruction conventions - - - - - - - - - - - - - - - - - 144

2.4.1 Operands - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 144

2.4.2 Operations - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 144

2.4.3 Abbreviations - - - - - - - - - - - - - - - - - - - - - - - - - - - - 145

PROGRAMMING MANUAL

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2.4.4 Data addressing modes - - - - - - - - - - - - - - - - - - - - - - 145

2.4.5 Instruction format - - - - - - - - - - - - - - - - - - - - - - - - - - 145

2.4.6 Flag states - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 146

2.4.7 Repeated instruction syntax - - - - - - - - - - - - - - - - - - - - 146

2.4.8 Shift value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 147

2.5 MAC instruction descriptions - - - - - - - - - - - - - - - - - 147

3 Revision History - - - - - - - - - - - - - - - - - - - - - - 195

PROGRAMMING MANUAL

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Introduction

This programming manual details the instruction set for the ST10 family of products. The

manual is arranged in two sections. Section 1 details the standard instruction set and

includes all of the basic instructions. Section 2 details the extension to the instruction set

provided by the MAC. The MAC instructions are only available to devices containing the

MAC, refer to the datasheet for device-specific information.

In the standard instruction set, addressing modes, instruction execution times, minimum

state times and the causes of additional state times are defined. Cross reference tables of

instruction mnemonics, hexadecimal opcode, address modes and number of bytes, are

provided for the optimization of instruction sequences. Instruction set tables ordered by

functional group, can be used to identify the best instruction for a given application.

Instruction set tables ordered by hexadecimal opcode can be used to identify specific

instructions when reading executable code i.e. during the de-bugging phase. Finally, each

instruction is described individually on a page of standard format, using the conventions

defined in this manual. For ease of use, the instructions are listed alphabetically.

The MAC instruction set is divided into its 5 functional groups: Multiply and

Multiply-Accumulate, 32-Bit Arithmetic, Shift, Compare and Transfer Instructions. Two new

addressing modes supply the MAC with up to 2 new operands per instruction. Cross

reference tables of MAC instruction mnemonics by address mode, and MAC instruction

mnemonic by functional code can be used for quick reference. As for the standard instruction

set, each instruction has been described individually in a standard format according to

defined conventions. For convenience, the instructions are described in alphabetical order.

PROGRAMMING MANUAL Standard Instruction Set

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1 Standard Instruction Set

1.1 Addressing modes

1.1.1 Short adressing modes

The ST10 family of devices use several powerful addressing modes for access to word, byte

and bit data. This section describes short, long and indirect address modes, constants and

branch target addressing modes.

Short addressing modes use an implicit base offset address to specify the 24-bit physical

address.

Short addressing modes give access to the GPR, SFR or bit-addressable memory space

Note: for byte GPRs, for word GPRs.

Mnemo Physical Address Short Address Range Scope of Access

Rw (CP) + 2*Rw Rw = 0...15 GPRs (Word) 16 values

Rb (CP) + 1*Rb Rb = 0...15 GPRs (Byte) 16 values

reg 00’FE00h + 2*reg reg = 00h...EFh SFRs (Word, Low byte)

00’F000h + 2*reg reg = 00h...EFh ESFRs (Word, Low byte)

(CP) + 2*(reg^0Fh) reg = F0h...FFh GPRs (Word) 16 values

(CP) + 1*(reg^0Fh) reg = F0h...FFh GPRs (Bytes) 16 values

bitoff 00’FD00h + 2*bitoff bitoff = 00h...7Fh RAM Bit word offset 128 values

00’FF00h + 2*(bitoff^FFh) bitoff = 80h...EFh SFR Bit word offset 128 values

(CP) + 2*(bitoff^0Fh) bitoff = F0h...FFh GPR Bit word offset 16 values

bitaddr Word offset as with bitoff. bitoff = 00h...FFh Any single bit

Immediate bit position. bitpos = 0...15

Table 1 Short addressing mode summary

PhysicalAddress BaseAddress ShortAddress+=

1=

2=

Standard Instruction Set PROGRAMMING MANUAL

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1.1.2 Long addressing mode

Long addressing mode uses one of the four DPP registers to specify a physical 18-bit or

24-bit address. Any word or byte data within the entire address space can be accessed in

this mode. All devices support an override mechanism for the DPP addressing scheme (see

section 1.1.3).

Note Word accesses on odd byte addresses are not executed, but rather trigger a

hardware trap. After reset, the DPP registers are initialized so that all long

addresses are directly mapped onto the identical physical addresses, within

segment 0.

Rw, Rb: Specifies direct access to any GPR in the currently active context (register bank). Both

'Rw' and 'Rb' require four bits in the instruction format. The base address of the current

address relative to the base address (CP), while 'Rb' specifies a 4 bit byte GPR address

relative to the base address (CP).

reg: Specifies direct access to any (E)SFR or GPR in the currently active context (register

bank). 'reg' requires eight bits in the instruction format. Short 'reg' addresses from 00h to

EFh always specify (E)SFRs. In this case, the factor '' equals 2 and the base address is

00’F000h for the standard SFR area, or 00’FE00h for the extended ESFR area. ‘reg’

accesses to the ESFR area require a preceding EXT*R instruction to switch the base

address. Depending on the opcode of an instruction, either the total word (for word opera-

tions), or the low byte (for byte operations) of an SFR can be addressed via 'reg'. Note that

the high byte of an SFR cannot be accessed by the 'reg' addressing mode. Short 'reg'

addresses from F0h to FFh always specify GPRs. In this case, only the lower four bits of

'reg' are significant for physical address generation, therefore it can be regarded as identi-

cal to the address generation described for the 'Rb' and 'Rw' addressing modes.

bitoff: Specifies direct access to any word in the bit-addressable memory space. 'bitoff' requires

eight bits in the instruction format. Depending on the specified 'bitoff' range, different base

addresses are used to generate physical addresses: Short 'bitoff' addresses from 00h to

7Fh use 00’FD00h as a base address, therefore they specify the 128 highest internal RAM

word locations (00’FD00h to 00’FDFEh). Short 'bitoff' addresses from 80h to EFh use

00’FF00h as a base address to specify the highest internal SFR word locations (00’FF00h

to 00’FFDEh) or use 00’F100h as a base address to specify the highest internal ESFR

word locations (00’F100h to 00’F1DEh). ‘bitoff’ accesses to the ESFR area require a pre-

ceding EXT*R instruction to switch the base address. For short 'bitoff' addresses from F0h

to FFh, only the lowest four bits and the contents of the CP register are used to generate

the physical address of the selected word GPR.

bitaddr: Any bit address is specified by a word address within the bit-addressable memory space

(see 'bitoff'), and by a bit position ('bitpos') within that word. Thus, 'bitaddr' requires twelve

bits in the instruction format.

PROGRAMMING MANUAL Standard Instruction Set

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Long addresses (16-bit) are treated in two parts. Bits 13...0 specify a 14-bit data page offset,

and bits 15...14 specify the Data Page Pointer (1 of 4). The DPP is used to generate the

physical 24-bit address (see figure below).

All ST10 devices support an address space of up to 16 MByte, so only the lower ten bits of

the selected DPP register content are concatenated with the 14-bit data page offset to build

the physical address.

The long addressing mode is referred to by the mnemonic “mem”.

Figure 1 Interpretation of a 16-bit long address

Mnemo Physical Address Long Address Range Scope of Access

mem (DPP0) || mem^3FFFh 0000h...3FFFh Any Word or Byte

(DPP1) || mem^3FFFh 4000h...7FFFh

(DPP2) || mem^3FFFh 8000h...BFFFh

(DPP3) || mem^3FFFh C000h...FFFFh

mem pag || mem^3FFFh 0000h...FFFFh (14-bit) Any Word or Byte

mem seg || mem 0000h...FFFFh (16-bit) Any Word or Byte

Table 2 Summary of long address modes

15 14 13

16-bit Long Address

DPP0

DPP1

DPP2

DPP3

14-bit page offset

24-bit Physical Address

selects Data Page Pointer

023 1314

Standard Instruction Set PROGRAMMING MANUAL

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1.1.3 DPP override mechanism

The DPP override mechanism temporarily bypasses the DPP addressing scheme.

The EXTP(R) and EXTS(R) instructions override this addressing mechanism. Instruction

EXTP(R) replaces the content of the respective DPP register, while instruction EXTS(R)

concatenates the complete 16-bit long address with the specified segment base address.

The overriding page or segment may be specified directly as a constant (#pag, #seg) or by a

word GPR (Rw).

Figure 2 Overriding the DPP mechanism

15 14 13

16-bit Long Address

#pag 14-bit page offset

24-bit Physical Address

16-bit Long Address

#seg 16-bit segment offset

24-bit Physical Address

EXTP(R):

EXTS(R):

PROGRAMMING MANUAL Standard Instruction Set

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1.1.4 Indirect addressing modes

Indirect addressing modes can be considered as a combination of short and long

addressing modes. In this mode, long 16-bit addresses are specified indirectly by the

contents of a word GPR, which is specified directly by a short 4-bit address ('Rw'=0 to 15).

Some indirect addressing modes add a constant value to the GPR contents before the long

16-bit address is calculated. Other indirect addressing modes allow decrementing or

incrementing of the indirect address pointers (GPR content) by 2 or 1 (referring to words or

bytes).

In each case, one of the four DPP registers is used to specify the physical 18-bit or 24-bit

addresses. Any word or byte data within the entire memory space can be addressed

indirectly. Note that EXTP(R) and EXTS(R) instructions override the DPP mechanism.

Instructions using the lowest four word GPRs (R3...R0) as indirect address pointers are

specified by short 2-bit addresses.

Word accesses on odd byte addresses are not executed, but rather trigger a hardware trap.

After reset, the DPP registers are initialized in a way that all indirect long addresses are

directly mapped onto the identical physical addresses.

Physical addresses are generated from indirect address pointers by the following algorithm:

1 Calculate the physical address of the word GPR which is used as indirect address

pointer, by using the specified short address ('Rw') and the current register bank base

address (CP).

2 Pre-decremented indirect address pointers (‘-Rw’) are decremented by a

data-type-dependent value ( for byte operations, for word operations),

before the long 16-bit address is generated:

3 Calculate the long 16-bit address by adding a constant value (if selected) to the content

of the indirect address pointer:

Long Address = (GPR Pointer) + Constant

4 Calculate the physical 18-bit or 24-bit address using the resulting long address and the

corresponding DPP register content (see long 'mem' addressing modes).

Physical Address = (DPPi) + Page offset

5 Post-Incremented indirect address pointers (‘Rw+’) are incremented by a

data-type-dependent value ( for byte operations, for word operations):

GPRAddress CP=2+ShortAddressoptionalstep!;–

1=

2=

GPRAddressGPRAddress=optionalstep!;–

1=

2=

GPRPointerGPRPointer=optionalstep!;+

Standard Instruction Set PROGRAMMING MANUAL

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The following indirect addressing modes are provided:

1.1.5 Constants

The ST10 Family instruction set supports the use of wordwide or bytewide immediate

constants. For optimum utilization of the available code storage, these constants are

represented in the instruction formats by either 3, 4, 8 or 16 bits. Therefore, short constants

are always zero-extended, while long constants can be truncated to match the data format

required for the operation (see table below):

Note Immediate constants are always signified by a leading number sign “#”.

Mnemonic Notes

[Rw] Most instructions accept any GPR (R15...R0) as indirect address pointer.

Some instructions, however, only accept the lower four GPRs (R3...R0).

[Rw+] The specified indirect address pointer is automatically incremented by 2 or 1 (for

word or byte data operations) after the access.

[-Rw] The specified indirect address pointer is automatically decremented by 2 or 1 (for

word or byte data operations) before the access.

[Rw+#data16]A 16-bit constant and the contents of the indirect address pointer are added

before the long 16-bit address is calculated.

Table 3 Table of indirect address modes

Mnemonic Word operation Byte operation

#data30000h+ data300h+ data3

#data40000h+ data400h+ data4

#data80000h+ data8data8

#data16 data16 data16 ^ FFh

#mask 0000h+ mask mask

Table 4 Table of constants

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