ST STM32H723 Bedienungsanleitung

Introduction

This application note is intended for system designers who develop applications based on STM32H723/33, STM32H725/35 and

STM32H730 microcontroller lines, and need an implementation overview of the following hardware features:

• Power supply

• Package selection

• Clock management

• Reset control

• Boot mode settings

• Debug management.

This document describes the minimum hardware resources required to develop an application based on STM32H723/33,

STM32H725/35 and STM32H730 microcontrollers.

Reference documents

•STM32H72x and STM32H73x datasheets

•STM32H723/733, STM32H725/735 and STM32H730 advanced Arm®-based 32-bit MCUs (RM0468)

•STM32H723/733, STM32H725/735 and STM32H730 errata sheet (ES0491)

The following documents are available on www.st.com website.

•Oscillator design guide for STM8S, STM8A and STM32 microcontrollers application note (AN2867)

•STM32 microcontroller system memory boot mode application note (AN2606).

Getting started with STM32H723/733, STM32H725/735 and STM32H730 Value

Line hardware development

AN5419

AN5419 - Rev 2 - May 2020

For further information contact your local STMicroelectronics sales office.

www.st.com

1General information

This document applies to STM32H723/33, STM32H725/35 and STM32H730Arm®-based microcontroller lines.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

AN5419

General information

AN5419 - Rev 2 page 2/50

2Power supplies

2.1 Introduction

The STM32H723/33, STM32H725/35 and STM32H730 are highly integrated microcontrollers that are based on

the Arm® Cortex®-M7 32-bit core (refer to the datasheets/databriefs for details).

The STM32H723/33, STM32H725/35 and STM32H730 microcontrollers require at least one single power supply

to be fully operational.

Additional power supplies or voltage references are required for some use cases. The general design guidelines

are explained in the following sections. The figure below illustrates the power supply layout.

In all the diagrams, the gray boxes represent power domains.

AN5419

Power supplies

AN5419 - Rev 2 page 3/50

Figure 1. Power supplies

BKUP

IOs

VDD domain

Analog domain

Core domain (VCORE)

Backup domain

D3 domain

(System

logic,

EXTI,

Peripherals,

RAM)

D1 domain

(CPU, peripherals,

RAM)

Level shifter

OPAMP,

Comparator

Voltage

regulator

ADC, DAC

Flash

D2 domain

(peripherals,

RAM)

Power

switch

Power switch

Step

Down

Converter

VCAP

VSS

VDDLDO

VDDSMPS

VLXSMPS

VSSSMPS

VFBSMPS

VBAT

VDDA

VREF+

VREF-

VSSA

Backup

regulator

VDD

Backup

RAM

Power

switch

HSI, CSI,

HSI48,

HSE, PLLs

IOs

Power

switch

USB

regulator

VDD50USB

VDD33USB

VSS

REF_BUF

VSS

logic

VREF+

USB

IOs

VSS

VSW

LSI, LSE, RTC,

Wakeup logic,

backup

registers, Reset

logic

VBKP

VBAT

charging

VREF-

USB regulator

VDD50USB

VDD33USB

USB

FS IOs

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Introduction

AN5419 - Rev 2 page 4/50

Note: VDDSMPS, VLXSMPS, VFBSMPS and VSSSMPS are available only on STM32H725/735 and STM32H730

devices.

Note: On STM32H723/733, VDDLDO is not available on a pin/ball. It is internally connected to VDD.

Table 1. PWR input/output signals connected to package pins/balls

Pin name Signal type Description

VDD Supply input Main I/O and VDD domain supply input.

VSS Supply input Main ground.

VDDA Supply input External analog power supply for analog peripherals.

VSSA Supply input Separated isolated ground for analog peripherals.

VBAT Supply input/output Backup battery supply: optional external supply for backup domain when VDD is not

present. Can also be used to charge the external battery.

VDDSMPS Supply input Supply for switch mode power supply (SMPS) step-down converter.

VLXSMPS Supply output SMPS step-down converter output.

VFBSMPS Supply regulation input SMPS feedback voltage sense.

VSSSMPS Supply input Ground for SMPS step-down converter.

VDDLDO Supply input Supply for the integrated low drop out regulator.

VCAP Supply input/output

Figure 2. System supply configuration shows the different possible regulator supply

configurations: using one, both or none.

Digital Core supply input / output pin. Is either provided by the embedded regulator or

from an external source.(1)

VDD50USB Supply input Supply for USB regulator.

VDD33USB Supply input/output Embedded USB regulator output or external USB supply when the internal regulator is

not used.

VREF+ Supply input/output Reference voltage for ADCs and DACs. Can be generated through the internal

VREFBUF or provided by an external source.

VREF- Supply input Ground reference for ADCs and DACs.

PDR_ON Digital input Control signal to switch the integrated POR/PDR circuitry ON/OFF.

1. Refer to Figure 2. System supply configuration for the different possible configurations

AN5419

Introduction

AN5419 - Rev 2 page 5/50

Figure 2. System supply configuration

External supply

VCORE

VCAP

VDDLDO

V reg

(on)

3. SMPS supplies LDO (No External supply)

VDDSMPS

VLXSMPS

VDD

SMPS

(on)

VSSSMPS

VFBSMPS

VSS

VCAP

VDDLDO

V reg

(on)

4. External SMPS supply, supplies LDO

VDD_extern

VDDSMPS

VLXSMPS

VDD

SMPS

(on)

VSSSMPS

VFBSMPS

VSS

VCORE

VCAP

VDDLDO

V reg

(off)

5. External SMPS Supply & Bypass

VDD_extern

VDDSMPS

VLXSMPS

VDD

SMPS

(on)

VSSSMPS

VFBSMPS

VSS

Ext

reg VCORE

6. Bypass

VCAP

VDDLDO

V reg

(off)

VDDSMPS

VLXSMPS

VDD

SMPS

(off)

VSSSMPS

VFBSMPS

VSS

VCORE

VCAP

VDDLDO

VDDSMPS

VLXSMPS SMPS

(off)

V reg

(on)

VDDLDO <= VDD

1. LDO Supply

VSSSMPS

VFBSMPS

VSS

VCORE

VDD

VCAP

VDDLDO

VDDSMPS

VLXSMPS

V reg

(off)

VDD

2. Direct SMPS Supply

SMPS

(on)

VSSSMPS

VFBSMPS

VSS

VCORE

VDD

VDD VDD

AN5419

Introduction

AN5419 - Rev 2 page 6/50

2.1.1 External power supplies and components

Refer to the STM32H72x and STM32H73x datasheets for more details on the electrical characteristics.

Table 2. Power supply connection

Package pin/

ball Voltage range External components Comments

VDD 1.62 to 3.6 V

100 nF ceramic, for each VDD as

close as possible of the pins. A 4.7 μF ceramic

connected to one of the VDD pin.

For VDD < 1.71 V the PDR must be disabled (see Section

2.2.1 Power-on reset (POR)/power-down reset (PDR))

VDDA

1.62 to 3.6 V

1 μF ceramic and 100 nF as close as possible

of the pin

VDDA can be connected to VDD through a ferrite bead.

1.8 to 3.6 V Restriction if a DAC or VREFBUF is used.

2.0 to 3.6 V Restriction if an OPAMP used.

0 to 3.6 V DAC, ADC, OPAMP, COMP, VREFBUF are not used.

VBAT 1.2 to 3.6 V 1 μF ceramic and 100 nF close to the VBAT pin

Can be connected directly to an external battery or

supply.

The external battery can be charged through the internal

5 kΩ or 1.5 kΩ resistor (see the reference manual

STM32H723/733, STM32H725/735 and STM32H730

advanced Arm®-based 32-bit MCUs (RM0468).

To be connected to VDD when not used.

When the PDR_ON pin is set to VSS the VBAT pin must

be connected to VDD since this functionality is no longer

available.

VDDSMPS

0 V No capacitor required. VDDSMPS connected to VSS when the converter is not

used.

1.62 to 3.6 V =

VDD Four different solutions are recommended:

• 10 μF (best cost trade-off), ESR 10mΩ

• 2x 10 μF (best area/performance trade-

off)

• 10 μF + 100 nF close from pin (best cost/

performance trade-off)

• 10 μF + 4.7 μF (best performance)

For SMPS supplying VCORE.

2.3 to 3.6 V =

VDD

For SMPS output regulated to 1.8 V.

The SMPS supplies the LDO regulator or an external

regulator.

3 to 3.6 V = VDD

For SMPS output regulated to 2.5 V.

The SMPS supplies the LDO regulator or an external

regulator.

VLXSMPS VCORE or 1.8 V

or 2.5 V

When the SMPS is used:

• 2.2 μH (DCR 110mΩ, Isat 1.7 A, Itemp

1.4 A) as close as possible to VLXSMPS.

• LQFP/BGA packages: 220 pF ceramic

capacitor on VLXSMPS.

• 2x 10 μF (ESR 5 mΩ) close to the

inductor on VFBSMPS connection side.

Depending on the use case, the SMPS provides the

digital core supply or a supply provided to another

regulator (external or internal LDO).

See Figure 2. System supply configuration for connection

VFBSMPS VCORE or 1.8 V

or 2.5 V -Refer to Figure 2. System supply configuration for the

use case dependent of this pin.

VDDLDO 1.62 to 3.6 V

When the LDO is used: 1x 4.7 μF capacitor

close to one VDDLDOx pin, all VDDLDOx pins

correctly connected together.

Otherwise: no capacitor is required. Connect

VDDLDOx to VDD.

VDDLDO ≤ VDD.

Up to three VDDLDO pins available depending on the

package specification.

AN5419

Introduction

AN5419 - Rev 2 page 7/50

Package pin/

ball Voltage range External components Comments

VCAP

VOS0/VOS1/

VOS2/VOS3/

SVOS3/SVOS4/

SVOS5

LDO enabled and SMPS enabled or disabled:

2.2 μF ESR < 100 mΩ for VCAP1

2.2 μF ESR < 100 mΩ for VCAP2

LDO disabled:

100 nF close to each VCAPx pin

VCAPx connected together

If the VCAP3 pin is available (depending on the

package), it must be connected to the other VCAP pins

but no additional capacitance is required.

In bypass mode the Vcore supply is externally provided

through the VCAPx pins.

VDD50USB 4.0 to 5.5 V 4.7 μF ceramic

Connected to an external supply or USB VBUS for an

internal USB regulator use case.

Connected to VDD33USB when the internal USB

regulator is not used (for packages having this pin

available).

VDD33USB

3.0 V to 3.6 V

1 μF ceramic and 100 nF ceramic (USB reg not

used)

1 μF max ESR 600 mΩ (USB reg used)

The VDD33USB supply can be provided externally or

through the internal USB regulator.

When the regulator is enabled its output will be provided

directly to the VDD33USB through the internal

connection.

This pin is internally tied to VDD when it is not present in

some specific packages. In consequence, the VDD

supply level must be compliant with VDD33 if the USB is

used for these packages.

0V to 3.6 V - When USB is not used.

VREF+

1.62 V to

≤ VDDA

1 μF ceramic and

100 nF ceramic close to the pin

or connected to VDDA through a resistor

(typically 47 Ω)

VREF+ is provided externally.

In some packages, the VREF+ pin is not available

(internally connected to VDDA).

2 V to

≤ VDDA

External VREF+ with VDDA>2 V and ADC used.

VREFBUF

reference

voltage

1 μF

VREF+ is provided by the embedded VREFBUF regulator.

Do not activate the internal VREFBUF when VREF+ is

provided externally

VREF- VSSA Tied to VSSA

Only available in some packages

Internally tied to VSSA when this pin is not present

PDR_ON VDD or VSS

Tied to VDD

Power-on reset (POR) and power-down reset (PDR)

circuit switched ON

Internally tied to VDD when this pin is not present in a

specific package.

VDD: 1.71 to 3.6 V

Tied to VSS

POR and PDR circuit switched off

VDD: 1.62 to 3.6 V

AN5419

Introduction

AN5419 - Rev 2 page 8/50

Figure 3. Power supply component layout

VDD

VDD33USB

VDD50USB

VREF-

VSSA

VSS

Analog domain

Core domain

Backup

domain

LDO

Voltage

regulator

Power switch

VDDLDO

VDDSMPS

VLXSMPS

VSSSMPS

VFBSMPS

VBAT

VDDA

VREF+

VDD

USB regulator

VCAP1/2

PDR_ON

POR/PDR

100 nF1 μF

100 nF

1 μF

STM32H723/733/

725/735/730

1 μF 1 μF 100 nF

47W

VDDA

Three different possible use cases

VREF+

100 nF

1 μF

Two different possible use cases

3.3V

Battery

100 nF

VDD

100 nF

4.7 μF

VDD

Two different possible use cases

100nF

100 nF

2.2 μF

LDO enabled LDO disabled

VCAP3

SMPS enabled SMPS disabled

10 μF 220 pF

10 μF

4.7 μ F

10 μF

VDD

2.2 μH

BKUP

IOs

VDD

IOs

VDD

domain

Refer to figure 2 for the use cases dependent

VDDLDO connections (no additional components)

Two different

possible use cases

4.7 μF

USB FS

IOs

SMPS

Switched Mode

Power Supply

step down

converter

Defines different use case options

Define power domaines

4.7 μF

LDO enabled

AN5419

Introduction

AN5419 - Rev 2 page 9/50

2.1.2 Digital circuit core supply (Vcore)

As shown in Figure 2. System supply configuration, the digital power can be supplied either by the internal linear

voltage regulator, the embedded SMPS step-down converter or directly by an external supply voltage (regulator

bypass). The SMPS step-down converter can also be cascaded with the linear voltage regulator.

In system Run mode, this digital core voltage can be set dynamically to the required performance (voltage scaling

VOS0 to VOS3).

In system Stop mode, the digital core voltage can be reduced to improve the power consumption (voltage scaling

SVOS3 to SVOS5).

For a detailed definition on the available power modes please read the power control (PWR) chapter of the

reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced Arm®-based 32-bit MCUs

(RM0468).

2.1.3 Independent analog supply and reference voltage

To improve analog peripheral performance, the analog peripherals feature an independent power supply which

can be separately filtered and shielded from noise on the PCB:

• The analog supply voltage input is available on a separate VDDA pin.

• An isolated ground connection is provided on the VSSA pin.

To ensure better ADC and DAC accuracy, the reference voltage can be provided externally through the VREF+

pin, this however is not available in all packages.

The VREF– pin is available on some packages to improve the ground noise immunity.

The VDDA minimum value (VDDA_MIN) depends on the analog peripheral and on whether a reference voltage is

provided or not, refer to Table 2. Power supply connection for more details.

2.1.4 Independent USB transceiver power supply

There are different ways to supply the USB transceivers, depending on VDD33USB and VDD50USB availability:

• When the VDD50USB pin is available, it can be used to supply an internal regulator dedicated to the USB

transceivers.

• In this case, either the USB VBUS or an external power supply can be used to provide the required voltage.

• The internal regulator output supply is connected to the USB FS PHY and is also available on the

VDD33USB pin (see Figure 1. Power supplies).

In this configuration, the VDD50USB voltage can rise either before or after the VDD power supply (see

Figure 6. VDD50USB power supply).

An external capacitor must be connected to VDD33USB (see Table 2. Power supply connection).

• When the VDD33USB pin is available, it can be used to supply the internal transceiver. In this case, the

VDD33USB pin should receive a voltage ranging between 3.0 to 3.6 V. If the VDD50USB pin is available

and the internal USB regulator is not used, VDD50USB must be connected with the VDD33USB pin. As an

example, when the device is powered at 1.8 V, an independent 3.3 V power supply can be applied to

VDD33USB.

When VDD33USB is connected to a separate power supply, it is independent from VDD and VDDA. In this case, it

must be the last supply to be turned on and the first supply to be switched off. The following conditions must be

respected (see Figure 5. VDD33USB connected to external power supply):

• During the power-on and power-down phases (VDD < VDD minimum value), VDD33USB should always be

lower than VDD.

• VDD33USB rising and falling time specifications must be adhered to (refer to table power-up/power-down

operating conditions for regulator on and table power-up/power-down operating conditions for regulator off

provided in the STM32H72x and STM32H73x datasheets).

• In operating mode, VDD33USB can be either lower or higher than VDD:

If a USB interface is used (USB OTG_HS / OTG_FS), the associated GPIOs powered by VDD33USB operate

between VDD33USB_MIN and VDD33USB_MAX(see Figure 5. VDD33USB connected to external power supply).

• On some packages neither the VDD33USB pin, nor the VDD50USB pin are available, it is the VDD pin

which supplies the VDD33USB through an internal connection.

• In this case, VDD is constrained by VDD33USB and must range between 3.0V and 3.6V

AN5419

Introduction

AN5419 - Rev 2 page 10/50

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