Tektronix TDS 520 Betriebsanleitung

1---

WARNING I

The following servicing instructions

are for use by qualified service

personnel only.

avoid personal

injury,

not perform any servicing

unless you are qualified

so.

Refer

the Safety Summary prior

performing any service.

Please

check

for

CHANGE INFORMATION

the

rear

this

manual.

Part No. 070-8313-00

Product Group 55

lHE

TDS520

DIGITIZING

OSCILLOSCOPE

Component Level

Diagnostic and

Repair Manual

Volume 2

COMMITTED

EJCCEL1.ENCE

DIGITALY REMASTERED

OUT OF PRINT- MANUAL SCAN

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,.---

WARRANTY

Tektronix warrants that this product will be free from defects

materials and workmanship for a period of three

(3)

years

from the date of shipment. If any such product proves defective during this warranty period, Tektronix,

its option, either

will repair the defective product without charge for parts and labor. or will provide a replacement in exchange for the

defective product.

order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the

warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for

packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges

prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country

which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges. duties. taxes.

and any other charges for products returned to any other locations.

This warranty shall not apply to any defect, failure or damage caused by improper use or improper

inadequate

maintenance and care. Tektronix shall not be obligated to furnish service under this warranty

repair damage resulting

from attempts

personnel other than Tektronix representatives to install, repair

service the product;

to repair

damage resulting from improper use

connection to incompatible equipment; or c) to service a product that has been

modified

integrated with other products when the effect

such modification or integration increases the time or

difficulty

servicing the product.

THIS WARRANTY

GIVEN

TEKTRONIX WITH RESPECT TO THIS PRODUCT IN LIEU OF ANY OTHER

WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES

OF MERCHANTABILITY

FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX' RESPONSIBILITY TO REPAIR

REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER

FOR BREACH

THIS

WARRANTY. TEKTRONIX AND ITS VENDORS WILL

NOT

LIABLE FOR ANY INDIRECT,

SPECIAL, INCIDENTAL,

CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX

THE

VENDOR

HAS

ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Instrument Serial Numbers

Each instrument manufactured

Tektronix has a serial number

a panel insert or tag, or stamped on the

chassis. The first letter

the serial number designates the country of manufacture. The last five digits of the

serial number are assigned sequentially and are unique to each instrument. Those manufactured

the United

States have six unique digits. The country of manufacture is identified as follows:

B010000

E200000

J300000

H700000

Tektronix, Inc., Beaverton, Oregon,

USA

Tektronix United Kingdom, Ltd., London

SonyfTektronix, Japan

Tektronix Holland,

NV,

Heerenveen,

The

Netherlands

Instruments manufactured for Tektronix

external vendors outside the United States

are

assigned a two digit

alpha code to identify the country of manufacture (e.g., JP for Japan,

for Hong Kong, IL for Israel, etc.).

Tektronix, Inc.,

P.O.

Box 500, Beaverton,

97077

Printed

U.S.A.

U.S.

and foreign

patents, issued and pending. The following are registered trademarks:

TEKTRONIX,

TEK,

TEKPROBE, SCOPEMOBILE and

Deskjet, HPGL, Laserjet and Thinkjet

are

products of the Hewlett-Packard Company.

Epson is a registered trademark of Epson America, Inc.

Interleaf is a trademark of Interleaf, Inc.

PostScript is a registered trademark of Adobe Systems, Inc.

'-:-,'

.~"'.

Vol.

2 Figure

Semiconductor Lead Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 Figure ii: Locating Components

Circuit Board

Schematic

Diagram.

. . . . . . . . . .

Vol.

2 v

A10 Acquisition

Vol. 2 Figure

9-1:

Attenuator Programming

........................................

Vol.

9-1

Vol. 2 Figure 9-2: A

Attenuator Board Programming Troubleshooting Procedure

........

Vol.

9-1

Vol. 2 Figure 9-3: Acquisition Digital Control Troubleshooting Procedure

................

Vol.

9-2

Vol. 2 Figure 9-4: Acquisition

ProcPs~or

fro.Jbleshooting Procedure

...................

Vol.

9-4

Vol. 2 Figure 9-5: Nonnal

Path

of the Vertical Channels

..............................

Vol.

9-5

Vol. 2 Figure 9-6:

Converter Troubleshooting Procedure

..........................

Vol.

9-5

Vol. 2 Figure 9-7: Analog

DAC

Control Troubleshooting Procedure

....................

Vol.

2 9-6

Vol. 2 Figure 9-8:

6 of U931.

U932. U933.

and U934

.............................

Vol.

9-7

Vol. 2 Figure 9-9:

TP903

(PCO)

..................................................

Vol.

9-7

Vol. 2 Figure 9-10:

TP906

(PC3). .

...............................................

Vol.

9-7

Vol. 2 Figure 9-11:

TP909

......................................................

Vol.

9-7

Vol. 2 Figure 9-12:

TP911

......................................................

Vol.

9-7

Vol. 2 Figure 9-13:

TP904

(PC1)

.................................................

Vol.

9-7

Vol. 2 Figure 9-14:

TP911

......................................................

Vol.

9-8

Vol. 2 Figure 9-15:

TP912

......................................................

Vol.

9-8

Vol. 2 Figure 9-16:

TP904

(PC1)

.................................................

Vol.

9-8

Vol. 2 Figure 9-17:

TP905

(PC2)

.................................................

Vol.

9-8

Vol. 2 Figure 9-18:

U601

pin 3

(PC7)

.............................................

Vol.

9-8

Vol. 2 Figure 9-19: Analog Holdoff

Trou~!~shC'oting

Procedure

........................

Vol.

9-9

Vol. 2 Figure 9-20: Analog Trigger Troubleshooting Procedure

........................

Vol.

9-11

Vol. 2 Figure 9-21:

AUX

1 Front

End

Troubleshooting Procedure .

.....................

Vol.

2 9-12

Vol. 2 Figure

9-22:

AUX

2 Front

End

Troubleshooting Procedure

.......................

Vol.

9-13

Vol. 2 Figure 9-23:

U1800

Pins

2,6,

and

with

kHz 1 Division Input

.............

Vol.

9-14

Vol. 2 Figure 9-24: C and DTrigger Troubleshooting Procedure

.......................

Vol.

9-14

Vol. 2 Figure 9-25:

Front

End

Troubleshooting Procedure

........................

Vol.

2 9-15

Vol.

2 Figure 9-26:

2 Front

End

Troubleshooting Procedure

........................

Vol.

9-16

Vol.

2 Figure 9-27: Clock System Troubleshooting Procedure

.........................

Vol.

2 9-17

Vol.

2 Figure 9-28: Reference Oscillator (U504 pin

...............................

Vol.

9-18

Vol. 2 Figure

9-29:

MHz

Loopback to the

VCO

(U504

13)

.......................

Vol.

9-18

Vol. 2 Figure

9-30:

Delay

Trigger·

Troubleshooting Procedure

.........................

Vol.

9-19

Vol. 2 Figure

9-31:

Demultiplexer Diagnostic Troubleshooting Procedure

...............

Vol.

2 9-20

Vol. 2 Figure

9-32:

Demultiplexer Screen Troubleshooting Procedure

..................

Vol.

9-21

TDS

520

Component

Level

Diagnostic

and

Repair

Manual

Contents

Vol.

2 Figure 9-33: Extended Trigger Troubleshooting Procedure

......................

Vol.

9-22

Vol.

2 Figure 9-34: Glitch Triggering

..............................................

Vol.

9-23

Vol.

2 Figure 9-35: Logic Trigger Troubleshooting Procedure

.........................

Vol.

9~24

Vol.

2 Figure 9-36: Time Interpolator Ramps

.......................................

Vol.

9-25

Vol.

2 Figure 9-37: Time Interpolator Troubleshooting Procedure

......................

Vol.

9-25

Vol.

2 Figure 9-38: Trigger Logic Failure Areas

.....................................

Vol.

9-26

Vol.

2 Figure 9-39: Trigger Logic Troubleshooting Procedure

.........................

. Vol. 2

9-26

Vol. 2 Figure 9-40: Probe Connection Troubleshooting Procedure

.....................

Vol.

9-27

Vol.

2 Figure 9-41: A

Acquisition Board (Section

Front)

..........................

. Vol. 2 9-28

Vol. 2 Figure 9-42:

A10

Acquisition Board (Section

Front)

..........................

. Vol. 2

9-29

Vol. 2

figure

9-43: A10 Acquisition Board (Section

Front)

..........................

. Vol. 2 9-30

Vol. 2 Figure 9-44: A10 Acquisition Board (Section

Front)

..........................

. Vol. 2

9-31

Vol.

2 Figure 9-45: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2 9-32

Vol. 2 Figure 9-46: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2

9-33

Vol. 2 Figure 9-47: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2 9-34

Vol. 2 Figure 9-48: A10 Acquisition Board (Section

Back)

..........................

. Vol. 2 9-35

10 Acquisition Component Locator

...............................................

Vol.

2 9-36

Vol.

2 Figure 9-49: A

Acquisition Waveforms

....................................

Vol.

2 9-40

DRAM Processor/Display

Vol.

2 Figure 9-50: Bdsack Troubleshooting Procedure

.......................

. . . . . .

Vol. 2 9-42

Vol. 2 Figure 9-51: BootROM Control Troubleshooting Procedure

.......................

Vol. 2

9-43

Vol. 2 Figure 9-52: Bus Control Register Troubleshooting Procedure

....................

Vol. 2 9-44

Vol. 2 Figure

9-5.3:

Byte Enable Decoder Troubleshooting Procedure. . . . . . . . . . . . . . . . . .

Vol.

2 9-45

Vol. 2 Figure 9-54:

CPU

Troubleshooting Procedure

.................................

Vol.

2 9-46

Vol.

2 Figure 9-55: Bus

Error

Circuitry Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol. 2

9-47

Vol.

2 Figure 9-56:

CPU

Bus Error Troubleshooting Procedure

.........................

Vol. 2

9-47

Vol.

2 Figure 9-57:

CPU

DIP

Switch Troubleshooting Procedure

........................

Vol.

9-48

Vol.

2 Figure 9-58: U1069 Signals When the

CPU

Forcefully Accesses the

DSP

(U1097) Bus

Vol.

9-49

Vol. 2 Figure 9-59:

CPU

Forced Bus From

DSP

Troubleshooting Procedure

..............

Vol.

9-49

Vol.

2 Figure 9-60: U1069 Signals During

Implicit

DSP

(U1097)

Bus

Access

the

CPU

Vol.

9-50

Vol.

2 Figure 9-61:

CPU

Implicit Bus From

DSP

Troubleshooting Procedure

..............

Vol.

2 9-50

Vol.

2 Figure 9-62:

CPU

Interrupt Troubleshooting Procedure

..........................

Vol. 2

9-51

Vol.

2 Figure 9-63:

CPU

LED

Troubleshooting Procedure

.............................

Vol.

2 9-52

Vol.

2 Figure 9-64: U1069 Signals When

tRe

CPU

Requests Access to the

DSP

(U1097)

Bus

Vol.

9-53

Vol.

2 Figure 9-65:

CPU

Request Bus From

DSP

Troubleshooting Procedure

.............

Vol.

9-53

"--"

Vol.

2 Figure 9-66:

Memory Troubleshooting Procedure

............................

Vol.

9-54

Vol.

2 Figure

9-67:

Display Reset Register Troubleshooting Procedure . . . . . . . . . . . . . . . .

Vol.

9-55

Vol.

2 Figure

9-68:

Dsack Troubleshooting Procedure . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .

Vol.

9-56

Vol.

2 Figure

9-69:

DSP

Troubleshooting Procedure. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .

Vol.

9-57

Vol.

2 Figure

9-70:

DSP

Dsack Troubleshooting Procedure

...........................

Vol.

9-58

Vol.

2 Figure

9-71:

DSP

Instruction Memory Troubleshooting Procedure

.................

Vol.

9-59

Vol.

2 Figure

9-72:

DSP

Interrupt Troubleshooting Procedure

..........................

Vol.

9-60

Vol.

2 Figure

9-73:

DSP

Memory Access Troubleshooting Procedure

....................

Vol.

9-61

Vol.

2 Figure

9-74:

DRAM

Control Troubleshooting Procedure

.........................

Vol.

9-62

Vol.

2 Figure

9-75:

Reset

Ul110 at Power

....................................

Vol.

9-63

Vol.

2 Figure

9-76:

Ull10

Bus

Interface signals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-63

Vol.

2 Figure

9-77:

UlllO

Output Control Signals

...................................

Vol.

9-63

Vol.

2 Figure

9-78:

Typical

DRAM

Dsack Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-64

Vol.

2 Figure

9-79:

DRAM

Dsack Signals During Refresh

.............................

Vol.

9-64

Vol.

2 Figure

9-80:

DRAM

Dsack Troubleshooting Procedure

..........................

Vol.

9-64

Vol.

2 Figure

9-81:

DUART

Troubleshooting Procedure

...............................

Vol.

9-65

Vol.

2 Figure

9-82:

FIFO

Troubleshooting Procedure

.................................

Vol.

9-66

Vol.

2 Figure

9-83:

GPIB

Troubleshooting Procedure

...

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 9-67

Vol. 2 Figure

9-84:

............................

Vol.

9-68

Vol. 2 Figure

9-85:

Kernel

Troubleshooting Procedure

.. . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-69

Vol.

2 Figure

9-86:

Kernel

Control Signals

..........................................

Vol.

2 9-70

Vol.

2 Figure

9-87:

Reset

.......................................................

Vol.

9-70

Vol.

2 Figure

9-88:

Kernel

Dsack Signals

..........................................

Vol.

9-71

Vol.

2 Figure

9-89:

Kernel

Dsack Troubleshooting Procedure

........................

Vol.

9-71

Vol.

2 Figure

9-90:

Kernel

RAM

Troubleshooting Procedure

.....

".....................

Vol.

2 9-72

Vol.

2 Figure

9-91:

Ul107

(NVRAM)

Control Signals

.................................

Vol.

9-73

Vol.

2 Figure

9-92:

NVRAM

Troubleshooting Procedure

...............................

Vol.

9-73

Vol.

2 Figure

9-93:

On/Standby Troubleshooting Procedure

........................

Vol.

2 9-74

Vol.

2 Figure

9-94:

Pixel Processor Register Troubleshooting Procedure

..........

". . . .

Vol.

2 9-75

Vol.

2 Figure

9-95:

RamDac Troubleshooting Procedure

..............................

Vol.

2 9-76

Vol.

2 Figure

9-96:

Random Dot Mode Troubleshooting Procedure

Vol.

9-77

Vol.

2 Figure

9-97:

Rasterizer Troubleshooting Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-78

Vol.

2 Figure

9-98:

Rasterizer Mode Troubleshooting Procedure

.....................

Vol.

9-79

Vol.

2 Figure

9-99:

Reset and

VCC

........................

...........

..........

Vol.

9-80

Vol.

2 Figure

9-100:

Reset Troubleshooting Procedure

...........................

...

Vol.

9-80

Vol.

2 Figure

9-101:

Text

Memory Troubleshooting Procedure . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-81

Vol.

2 Figure

9-102:

Timer Interrupt Troubleshooting Procedure

........................

Vol.

9-82

Vol.

2 Figure

9-103:

Vector List Memory Troubleshooting Procedure

....................

Vol.

9-83

Vol.

2 Figure

9-104:

Video Troubleshooting Procedure

...............................

Vol.

9-84

Vol.

2 Figure

9-105:

Video

Out

Signal

.............................................

Vol.

9-85

Vol.

2 Figure

9-106:

VSC

.........................

Vol.

9-86

Vol.

2 Figure

9-107:

Waveform Memory Troubleshooting Procedure . . . . . . . . . . . . . . . . . . .

Vol.

9-87

Vol.

2 Figure

9-108:

Mode Troubleshooting Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

9-88

Vol.

2 Figure

9-109:

All

DRAM

Processor/Display

Boar~

(Section

...................

Vol.

9-89

TDS

520

Component

Level

Diagnostic

and Repair

Manual

------~~~~~~

--~-

-~-~~-

Vol.

2 Figure 9-110: A

DRAM

Processor/Display Board (Section

..................

Vol.

2 9-90

Vol.

2 Figure 9-111: A

DRAM

Processor/Display Board (Section

..................

Vol.

9-91

Vol.

2 Figure 9-112: A

DRAM

Processor/Display Board (Section

..................

Vol.

9-92

DRAM

Processor/Display Component Locator

...................................

Vol.

9-93

Vol.

2 Figure 9-113: A

DRAM

Processor/Display Waveforms

........................

Vol.

9-96

Front Panel

Vol.

2 Figure 9-114: A12

Front

Panel System Troubleshooting Procedure

...............

Vol.

2 9-97

Vol.

2 Figure 9-115:

PC1

and PC2 Timing

.........................................

Vol.

2 9-98

Vol.

2 Figure 9-116: PC5 Timing

.................................................

Vol.

9-98

Vol.

2 Figure 9-117:

PCO

Timing

.................................................

Vol.

2 9-98

Vol.

2 Figure 9-118:

PCO

Timing

.................................................

Vol.

2 9-98

Vol. 2 Figure 9-119: Row

1-8

Timing

.............................................

. Vol. 2 9-98

Vol.

2 Figure 9-120: Row

1-8

Timing

.............................................

Vol.

2 9-98

Vol. 2 Figure 9-121: Bell Troubleshooting Procedure,

................................

Vol.

2 9-99

Vol.

2 Figure 9-122: Front Panel

LED

Troubleshooting Procedure

......................

Vol.

2 9-100

Vol.

2 Figure 9-123: Front Panel

LED

Test Loop Waveforms

..........................

Vol.

9-101

Vol.

2 Figure 9-124: Front Panel

LED

Test

Loop Troubleshooting Procedure

.............

Vol.

9-101

Vol.

2 Figure 9-125: Front Panel Mux Test Loop Waveforms

..........................

Vol.

2 9-102

Vol.

2 Figure 9-126: Front Panel Mux

Test

Loop Troubleshooting Procedure

.............

Vol.

2 9-102

Vol.

2 Figure 9-127: Front Panel Processor Troubleshooting Procedure

.................

Vol.

2 9-103

Vol. 2 Figure 9-128: PC2

(TP20)

Timing Signal During the Front Panel Self Diagnostic

Loop.

Vol.

2 9-104

Vol.2

Figure 9-129: Front Panel Self Diagnostic Loop Troubleshooting Procedure

........

Vol.

2 9-104

Vol.2

Figure 9-130: Front Panel Switch

Test

Loop Waveforms

........................

Vol.

2 9-105

Vol.

2 Figure 9-131: Front Panel Switch Test Loop Troubleshooting Procedure

...........

Vol.

2 9-105

Vol. 2 Figure 9-132: Probe Compensator Troubleshooting Procedure

...................

. Vol. 2 9-106

Vol. 2 Figure 9-133: A12

Front

Panel Board (Front)

..................................

Vol.

2 9-107

Vol.

2 Figure 9-134: A12

Front

Panel Board (Back)

..................................

Vol.

2 9-108

A12 Front Panel Component Locator

..............................................

Vol.

2 9-109

Vol. 2 Figure 9-135: A12

Front

Panel Waveforms

...................................

Vol.

2 9-110

Firmface

Vol. 2 Figure 9-136: Firmface Troubleshooting Procedure

...................

. . . . . . . .

Vol.

9-111

Vol. 2 Figure 9-137: A

Firmface Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 9-112

Firmface Component Locator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vol.

2 9-113

Vol.2

A14

Bus

Vol.

2 Figure 9-138: A

Bus Board . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .

Vol.

2 9-114

Bus Component Locator

...................................................

Vol.

9-115

A15 Attenuator

Vol. 2 Figure 9-139: Attenuator Troubleshooting Procedure. . . . . . .. . . . . . . . . . . . . . . . . . .

Vol.

2 9-116

Vol. 2 Figure 9-140: Attenuator Hybrid

.............................................

Vol.

2 9-117

Vol. 2 Figure 9-141: A15 Attenuator Board

.........................................

Vol.

9-118

A15 Attenuator Component Locator

................................................

Vol. 2

9-119

A16 (A17, A18, A19) Low Voltage Power

Supply

Vol. 2 Figure 9-142: A16 Low Voltage Power Supply Module Isolation Troubleshooting

Procedure

...........................................................

. Vol. 2 9-120

Vol. 2 Figure 9-143: Boost Control Troubleshooting Procedure

........................

. Vol. 2

9-121

Vol. 2 Figure 9-144:

and Q6 Gate Drive Wavefonns

..............................

. Vol. 2 9-122

Vol. 2 Figure 9-145:

FEr

DRIVE

Wavefonn

........................................

Vol.

2 9-122

Vol. 2 Figure 9-146: LowVoltage Power Supply Troubleshooting Procedure

.............

. Vol. 2 9-123

Vol. 2

Vol. 2 Figure 9-147: Main Converter Control Troubleshooting Procedure

................

Figure 9-148: Q7 and Q8

GATE

DRIVE

......................................

Vol.

2 9-124

Vol. 2 9-125

Vol. 2 Figure 9-149:

GATE

DRIVE

................................................

. Vol. 2 9-125

Vol. 2 Figure 9-150:

Pin 7

...................................................

Vol.

2 9-125

Vol. 2 Figure 9-151: Q5 and

Gate Drive

........................................

. Vol. 2 9-126

Vol. 2 Figure 9-152: Power Supply Primary Troubleshooting Procedure

.................

Vol.

2 9-126

Vol. 2 Figure 9-153: Q7 and

Gate Drive

........................................

. Vol. 2 9-127

Vol.

2 Figure 9-154: Power Supply Secondary Troubleshooting Procedure

..............

Vol.

2 9-127

Vol.

2 Figure 9-155: A17 Main

Power Supply Board (Section

.....................

. Vol. 2 9-128

lDS

520

Component

Level

Diagnostic

and Repair

Manual

Vol.

2 Figure 9-156: A

Main

Power Supply Board (Section

.....................

. Vol. 2 9-129

Vol.

2 Figure 9-157:

A17

Main

Power Supply Board (Section

....................

. Vol. 2 9-130

Vol.

2 Figure 9-158: A

Main

Power Supply Board (Section

....................

. Vol. 2

9-131

Main

Power Supply Component Locator

.....................................

. Vol. 2 9-132

Vol.

2 Figure 9-159:

A17

Main

Power Supply Waveforms

..........................

. Vol. 2 9-133

Vol.

2 Figure 9-160: A

Main Converter Control Board

..............................

. Vol. 2 9-136

Main Converter Control Component Locator

.....................................

. Vol. 2 9-137

Vol.

2 Figure 9-161: A

Main Converter Control Waveforms

.........................

. Vol. 2 9-138

Vol.

2 Figure 9-162: A

Power Factor Control Board

...............................

. Vol. 2 9-139

Power Factor Control Component Locator

......................................

. Vol. 2 9-140

A20 CRT Driver

Vol.

2 Figure 9-163: Display Distortion Troubleshooting Procedure

.....................

. Vol. 2

9-141

Vol.

2 Figure 9-164: Display Driver Troubleshooting Procedure

........................

. Vol. 2 9-142

Vol. 2 Figure 9-165: Video, Sync, and Scan Troubleshooting Procedure

................

. Vol. 2 9-143

Vol.

2 Figure 9-166:

A20

eRT Driver Board

........................................

. Vol. 2 9-144

A2.0

CRT

Driver Component Locator

...............................................

. Vol. 2 9-145

Vol. 2 Figure 9-167:

A2.0

eRT Driver Waveforms

....................................

. Vol. 2 9-146

A21

VCO Board

Vol. 2 Figure 9-168:

A2.1

veo

Board Vol. 2 9-149

A2.1

veo

Board Component Locator

...............................................

Vol. 2 9-150

Schematics and Block Diagrams

Vol.2

Iii

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