Texas Instruments TPS7H4003EVM Bedienungsanleitung
User's Guide
TPS7H4003EVM Evaluation Module (EVM)
ABSTRACT
The TPS7H4003EVM is the evaluation module (EVM) for the TPS7H4003-SEP and provides a platform to
electrically evaluate its features. This user's guide provides details about the EVM, its configuration, schematics,
and BOM.
Figure 1-1. TPS7H4003EVM (Single Channel)
Table of Contents
1 TPS7H4003EVM Overview..................................................................................................................................................... 3
2 TPS7H4003EVM Default Configuration.................................................................................................................................4
3 TPS7H4003EVM Initial Setup................................................................................................................................................. 5
4 TPS7H4003EVM Testing......................................................................................................................................................... 6
5 TPS7H4003EVM Schematic................................................................................................................................................. 10
6 TPS7H4003EVM Bill of Materials (BOM)............................................................................................................................. 11
7 Board Layout.........................................................................................................................................................................14
8 Support Resources...............................................................................................................................................................20
9 Revision History................................................................................................................................................................... 20
List of Figures
Figure 1-1. TPS7H4003EVM (Single Channel)........................................................................................................................... 1
Figure 4-1. Output Voltage Regulation........................................................................................................................................ 6
Figure 4-2. Output Voltage Ripple VIN = 5 V, VOUT = 1 V, IOUT = 18 A.................................................................................... 6
Figure 4-3. Output Soft Start Voltage, VIN = 5 V, VOUT = 1 V, IOUT = 18 A.............................................................................. 7
Figure 4-4. Transient Response to Load Step 9 A to 18 A at 1 A/µs........................................................................................... 7
Figure 4-5. Transient Response to Load Step 18 A to 9 A at 1 A/µs........................................................................................... 8
Figure 4-6. EVM Modification to Measure Frequency Response................................................................................................ 8
Figure 4-7. Frequency Response Test Setup.............................................................................................................................. 9
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Figure 4-8. Frequency Response................................................................................................................................................ 9
Figure 5-1. TPS7H4003EVM Schematic................................................................................................................................... 10
Figure 7-1. Top Overlay............................................................................................................................................................. 14
Figure 7-2. Top Solder............................................................................................................................................................... 14
Figure 7-3. Top Layer.................................................................................................................................................................15
Figure 7-4. Signal Layer One.....................................................................................................................................................15
Figure 7-5. Signal Layer Two.....................................................................................................................................................16
Figure 7-6. Signal Layer Three.................................................................................................................................................. 16
Figure 7-7. Signal Layer Four.................................................................................................................................................... 17
Figure 7-8. Signal Layer Five.....................................................................................................................................................17
Figure 7-9. Signal Layer Six...................................................................................................................................................... 18
Figure 7-10. Bottom Layer......................................................................................................................................................... 18
Figure 7-11. Bottom Solder........................................................................................................................................................ 19
Figure 7-12. Bottom Overlay......................................................................................................................................................19
Figure 7-13. Drill Drawing.......................................................................................................................................................... 20
Figure 7-14. PCB Dimensions................................................................................................................................................... 20
List of Tables
Table 2-1. Default EVM Configuration......................................................................................................................................... 4
Table 3-1. Summary of Connections............................................................................................................................................5
Table 6-1. TPS7H4003EVM BOM..............................................................................................................................................11
Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
Trademarks www.ti.com
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1 TPS7H4003EVM Overview
The TPS7H4003-SEP is a radiation hardened, 7-V, 18-A synchronous step-down converter with integrated high-
side and low-side MOSFETs. High efficiency and efficient usage of space are achieved through low resistance
MOSFETs and a current mode control implementation.
The EVM is configured in a default state to accept a 5-V input but can be modified to disable or change the
under voltage lock out (UVLO) protection, allowing for any input voltage from 3 V to 7 V. The EVM is also
configured for a 1-V output at a maximum peak output current of 18 A. Again, the regulated output voltage can
be modified by changing one resistor on the board. The TSP7H4003-SEP has a dedicated soft start, enable, and
adjustable slope compensation pins providing design flexibility to meet specific application requirements.
Finally, as shown in Figure 1-1, this EVM supports a single POL channel. However, the device does support
parallel operation. With four POLs operating in quadrature phases, a 72-A load current can theoretically be
provided.
1.1 Features
• 0.6-V ±1.6% voltage reference over temperature, radiation, and line and load regulation
• Adjustable slope compensation
• Adjustable soft start
• Adjustable input enable and undervoltage lockout (UVLO)
• Maximum output current of 18 A
1.2 Applications
• Point of load regulation
• Supports harsh environment applications
• Space satellite point of load supply for FPGAs, microcontrollers, data converters, and ASICs
• Space satellite payloads
• Radiation hardened applications
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2 TPS7H4003EVM Default Configuration
Table 2-1 describes the default configuration of the TPS7H4003EVM listing the external components that define
the converter design.
Table 2-1. Default EVM Configuration
PARAMETER SPECIFICATIONS DESCRIPTION
Input power supply 5 V Bound by UVLO enable circuit (R9, R10)
Regulated output voltage 1 V R6 (RTOP) = 10 kΩ, R7 (RBOTTOM) = 15.4 kΩ
LOUT 1.0 µH Chosen to meet inductor ripple current of 10% (Kind = 0.1)
COUT 2 mF
Chosen for (1) ESR = 1 mΩ to set output voltage ripple; (2)
value used during single event effects testing ensuring regulation
maintained with single event upset to switching
Output current 0 to 18 A By design
Switching frequency 500 kHz Set by R1 (RT) = 174 kΩ
Soft start time constant ≈2 ms Set by C16 (Css) = 10 nF
UVLO enable rising ≈4.432 V Set by R10 = 10 kΩ and R9 = 3.4 kΩ
UVLO enable falling ≈4.284 V Set by R10 = 10 kΩ and R9 = 3.4 kΩ
Loop bandwidth ≈30 kHz Set by operational transconductance amplifier (OTA) compensation
circuit: R7 (RCOMP) = 10 kΩ, C15 (CCOMP) = 10 nF, C14 (CHF) =
150 pF
Loop phase margin ≈60°
Gain margin ≈–25 dB
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3 TPS7H4003EVM Initial Setup
This section provides the test instruments required and the connections to the EVM.
1. Input DC power supply
a. Set for 5-V DC, 8-A current limit.
b. Connect positive output of DC supply to pin 1 of connector J1 (PVIN) and negative terminal of supply to
pin 2 of connector J1 for ground using 16 AWG wire or larger.
• NOTE: For more precise measurements, eliminating the IR voltage drop in the input cables is
achieved by using a power supply source with sensing ports and connecting between TP2 to PVIN
and TP1 to GND.
2. DC electronic load
a. Connect positive DC input of e-load to pin 1, VOUT, of connector J7 (VOUT) using 16 AWG wire.
• NOTE: Wire from pin 1, positive terminal of connector, to the e-load should include at least some part
in which the wire gauge can be strapped by the oscilloscope current probe. This will eliminate the
need for a setup change to cover all tests.
b. Connect negative DC input of e-load to pin 2, PGND, of connector J7 (VOUT) using 16 AWG wire.
c. Connect voltage monitoring sensing ports of e-load across test points TP12 (VOUT1) and TP13 (PGND).
A voltage meter can be used to monitor this voltage also.
3. Oscilloscope
a. CH1 - Connect voltage scope probe to scope probe test point J5 (PH) to monitor the phase node. DC
coupled, Full BW, 2 V/div, Rising Edge Trigger at 0.5 V.
b. CH2 - Connect voltage scope probe to scope probe test point J6 (VOUT) to monitor the output voltage.
AC coupled, BW = 20 MHz, 10 mV/div.
c. CH4 - Connect current scope probe to monitor current through wire connecting J7 (VOUT) and e-load. 5
A/div.
• NOTE: Only required for transient load testing.
Table 3-1. Summary of Connections
REFERENCE DESIGNATOR SILKSCREEN FUNCTION
J1 PVIN Input power: pin 1 = 5 V, pin 2 = GND (Vsupply)
J7 VOUT Output voltage: pin 2 = GND, pin 1 = Vout ≈1 V (e-load)
J5 PH Phase switching node scope probe test point (Scope CH-1)
J6 VOUT VOUT scope probe test point (Scope CH-2)
TP12 VOUT VOUT test point (e-load monitor)
TP2 PVIN PVIN test point (Vsupply_sense)
TP1, TP13 GND GND test points (Vsupply_sense, e-load monitor)
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4 TPS7H4003EVM Testing
The following tests will be described in subsequent sections.
•Section 4.1 Output voltage regulation
•Section 4.2 Output voltage ripple
•Section 4.3 Soft startup
•Section 4.4 Transient response to positive/negative load step (9 A to 18 A to 9 A)
•Section 4.5 Loop frequency response
4.1 Output Voltage Regulation
1. Turn-on input DC source (5 V).
2. Turn on the e-load and sweep load current from 0 A to 18 A. The monitored output voltage at TP12 (VOUT)
is at or near 1.0 V across the entire current load sweep as shown in Figure 4-1.
Figure 4-1. Output Voltage Regulation
4.2 Output Voltage Ripple
Display CH1 (PH) and CH2 (VOUT) [AC coupled, BW = 20 MHz] on oscilloscope to monitor the switching phase
node and the output voltage ripple as shown in Figure 4-2.
Figure 4-2. Output Voltage Ripple VIN = 5 V, VOUT = 1 V, IOUT = 18 A
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4.3 Soft Startup
Display CH1 (PH) and CH2 (VOUT) [DC coupled, 500 mV/div] on oscilloscope to monitor the switching phase
and the soft start profile of the output voltage as shown in Figure 4-3.
Figure 4-3. Output Soft Start Voltage, VIN = 5 V, VOUT = 1 V, IOUT = 18 A
4.4 Transient Response to Positive/Negative Load Step (9 A to 18 A to 9 A)
1. Configure e-load to switch between 9 A and 18 A at a rate of 1 A/µs.
2. On oscilloscope, display CH2 (VOUT) [AC coupled, 20 mV/div] and CH4 (Output Current Probe) [5 A/div,
trigger rising edge ≈12 A] with 40 µs/div.
Figure 4-4 shows the response to this load step to be less than 35 mV or –3.5%.
Figure 4-4. Transient Response to Load Step 9 A to 18 A at 1 A/µs
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3. Change the trigger on CH4 to falling edge to capture the transient response of VOUT to negative current
step from 18 A to 9 A as shown in Figure 4-5.
Figure 4-5. Transient Response to Load Step 18 A to 9 A at 1 A/µs
4.5 Loop Frequency Response
Measuring the frequency response of the feedback loop requires a unique test setup as well as physical
changes to the EVM. 0-Ω resistor jumper R8, below TP9 (BODE) test point and circled in yellow in the graphic
below, must be lifted in order to break the loop. Both test points TP9 (BODE) and TP10 (VOUT) will be used for
connections to the Bode100 instruments.
Figure 4-6. EVM Modification to Measure Frequency Response
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4.6 Setup
The test setup, which includes several connections to Picotest Bode100 test instruments, is shown in Figure 4-7
with measurement results shown in Figure 4-8. The CHF, high frequency pole, component of the compensation
circuit is optional. Omitting it will result in slightly increased phase margin. However, the benefit of including it is
that the gain curve is set in a downward trajectory as frequency increases, making a monotonic gain curve more
likely to be achieved.
Figure 4-7. Frequency Response Test Setup
Figure 4-8. Frequency Response
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