Texas Instruments UCC5390SCD Bedienungsanleitung

SLLU282A–December 2017–Revised February 2018

UCC5390SCD With Isolated Bias Supply

User's Guide

SLLU282A–December 2017–Revised February 2018

UCC5390SCD With Isolated Bias Supply

This manual describes the UCC5390SCD evaluation module (EVM). The UCC539SCD EVM is designed

to be embedded into a power system by attaching directly to the power FET or IGBT in both TO-220 or

TO-247 packages. This approach helps power system designers verify the performance of the UCC53x0x

drivers and the SN6505B-based bias supply during the early stage of the design in actual system

operating conditions.

WARNING

Although these devices provide galvanic isolation of up to 3000 V,

the EVM cannot be used for isolation voltage testing.

Voltage exceeding the EVM ratings (VCC1 > 15 V, VCC2 – VEE2 > 33 V,

and IGBT collector-emitter voltage VCE > 50 V) can damage the

EVM, and result in personal injury.

Contents

1 Introduction ................................................................................................................... 3

2 General Overview............................................................................................................ 3

3 Electrical Specifications..................................................................................................... 5

4 Detailed Description......................................................................................................... 5

5 Test Summary................................................................................................................ 8

6 Power Up, Capturing Waveforms, and Power Down.................................................................. 11

7 Bias Supply Performance ................................................................................................. 21

8 Bill of Materials ............................................................................................................. 24

9 Layout Diagrams ........................................................................................................... 25

10 References.................................................................................................................. 27

List of Figures

1 UCC5390SCDEVM-010 Functional Block Diagram..................................................................... 3

2 UCC5390SCDEVM-010 Board Image.................................................................................... 4

3 UCC5390SCDEVM-010 Electrical Schematic ........................................................................... 6

4 Soldering UCC5390SCDEVM-010 Board for System Level Evaluation ............................................ 10

5 Test Setup for UCC5390SCDEVM-010 System Level Evaluation................................................... 11

6 Gate-Source Driver Voltage .............................................................................................. 12

7 Expanded Gate-Source Drive Voltage Rise Time ..................................................................... 13

8 Expanded Gate-Source Drive Voltage Fall Time ...................................................................... 14

9 Inductor Current (Red), Drain-Source (Pink) and Gate-Source Drive Voltages (Blue and Green) at 800-V

Input, 0-A Output........................................................................................................... 15

10 Expanded Soft Switching Waveforms During Vds Rise............................................................... 16

11 Expanded Soft Switching Waveforms During Vds Fall................................................................ 17

12 Inductor Current (Red), Drain-Source (Pink) and Gate-Source Drive Voltages (Blue and Green) at 800-V

Input, 1.0-A Output......................................................................................................... 18

13 Expanded Hard, 71 V per ns Switching Waveforms During Vds Rise .............................................. 19

14 Expanded Soft, 3.4 V per ns Switching Waveforms During Vds Fall ............................................... 20

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15 Bias Supply Efficiency at Different Configurations..................................................................... 21

16 Bias Supply Regulation at Different Configurations ................................................................... 22

17 Bias Supply Secondary Side Switching Waveforms................................................................... 23

18 Top Solder Mask ........................................................................................................... 25

19 Top Layer ................................................................................................................... 25

20 Bottom Layer................................................................................................................ 25

21 Bottom Solder Mask ....................................................................................................... 26

22 Mechanical Dimensions ................................................................................................... 26

23 Assembly Drawings........................................................................................................ 27

List of Tables

1 Connection Descriptions.................................................................................................... 5

2 UCC5390SCDEVM-010 Electrical Specifications ....................................................................... 5

3 Bias Voltage Configurations................................................................................................ 7

4 Two-Channel Function Generator Settings .............................................................................. 9

5 Initial Oscilloscope Settings............................................................................................... 10

6 Bill of Materials ............................................................................................................. 24

Trademarks

All trademarks are the property of their respective owners.

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Introduction

SLLU282A–December 2017–Revised February 2018

UCC5390SCD With Isolated Bias Supply

1 Introduction

The UCC5390SCDEVM-010 device is a complete, single-channel, isolated gate driver board with a

reconfigurable bias supply, which provides a wide range of drive voltages. This EVM from TI is based on a

17-A, split output, basic insulation UCC5390SCD driver in a SOIC-8 package. The EVM also includes a

SN6505B-based bias supply that can be configured for single or split-rail drive voltage from 11 V to 33 V,

covering a wide range of Si and SiC FETs and IGBTs. Compact form factor, 1.5” × 0.83” × 0.3”, and

embedded footprints for TO-220 and TO-247 power device packages, allow for easy, direct connection to

FETs or IGBTs in the power system, for comprehensive performance evaluation

2 General Overview

The UCC5390SCDEVM-010 device uses a 17-A, split output driver, UCC5390SCD, and an SN6505B-

based bias supply. The EVM can be configured with or without split rail, for optimal drive voltages

depending on the specific application. By default, the bias supply is configured as a split-rail supply

providing 18-V turn ON and –4-V turn OFF, which is optimal for many SiC FETs. Figure 1 shows the block

diagram of the EVM.

Figure 1. UCC5390SCDEVM-010 Functional Block Diagram

General Overview

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Figure 2 shows the board image of the EVM.

Figure 2. UCC5390SCDEVM-010 Board Image

The EVM includes an isolated driver, UCC5390SCD, and bias supply, SN6505B. The UCC5390SCD

device is part of the UCC53xx family of drivers, in an 8-pin SOIC package including variants with different

pinout configurations and drive strengths. For this design, the UCC5390SCD device, with split output, 17-

A, and typical current capability, has been selected for its ability to optimally drive FETs and IGBTs in mid-

and high-power applications. The SN6505B device is a push-pull transformer driver, operating at 420 kHz

to provide a compact bias solution for isolated drivers, digital isolators, sense circuits, and various

communication buses. See the UCC53x0 3-kVRMS Single-Channel Isolated Gate Drivers data sheet and

SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet for more information

about the UCC5390 isolated driver and SN6505B transformer driver.

The primary side of the EVM is supplied by a 3-V to 5.5-V external voltage source. This voltage is

converted and isolated through a high-frequency transformer to provide bias voltage from 11-V up to 33-V

range to the secondary isolated side of the driver. Bias supply is an unregulated DC-DC transformer, so

the variation of primary voltage directly impacts the secondary side voltage. Therefore, TI recommends an

external voltage source regulated within 5% to 10% for this design. The driver has two inputs: inverted and

non-inverted. One input can be used for the PWM signal and the other as Enable. The driver has split

outputs that, through gate resistors, are connected to output holes to allow direct soldering to the power

device in TO-220 or TO-247 packages. The secondary side of the bias supply includes a rectifier circuit

that can be configured as center-tapped or bridge, therefore expanding the range of available bias

voltage. The secondary side also includes a circuit to generate a split rail with negative turn OFF bias for

applications and power devices where dv/dt-induced, spurious turn ON may be a potential issue.

2.1 Features

• Compact, isolated gate driver board for direct connection to power FETs and IGBTs in high-voltage,

mid-, and high-power converters and inverters

• Split output, 17-A, typical sink and source drive current for optimal turn ON and turn OFF settings

• Single or split rail bias supply configuration in 11-V to 33-V range

• Robust, noise-immune solution with CMTI > 100 V per ns

• Supports 3-kVrms basic isolation

• Provides up to 0.8-W drive power using 80% efficient bias supply

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General Overview

SLLU282A–December 2017–Revised February 2018

UCC5390SCD With Isolated Bias Supply

2.2 I/O Description

Table 1 lists the connection descriptions.

Table 1. Connection Descriptions

Pin Description

VCC1 VCC positive input. Powers driver and bias ICs, uses 3-V to 5.5-V range

GND1 Ground and reference plane, VCC, IN+, and IN– negative input

IN+ Non-inverting input of driver IC

IN– Inverting input of driver IC

S Source connection to external FET in TO-220 or TO-247 package

G Gate connection to external FET in TO-220 or TO-247 package

D Drain connection to external FET in TO-220 or TO-247 package

3 Electrical Specifications

Table 2 shows the electrical parameters of the UCC5390SCDEVM-010.

Table 2. UCC5390SCDEVM-010 Electrical Specifications

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

INPUT CONDITIONS

Primary input

supply voltage

(Vcc1)

3 5.5 V

Input signal rising

threshold 0.7 × Vcc1

Input signal falling

threshold 0.3 × Vcc1

OUTPUT CONDITIONS

Gate drive

voltage Depends on Vcc1 11 33 V

Source current 10 17 A

Propagation

delay 10 17 ns

Drive power At 25°C 0.8 W

SYSTEM CHARACTERISTICS

CMTI 100 V/ns

Basic isolation 3 kVrms

Capacitance

through isolation 5 pF

Operating

ambient –40 25 85

Board size Length × width × height 1.5 × 0.83 × 0.3 1.5 × 0.83 × 0.3 1.5 × 0.83 × 0.3 inch

Drive area size Length × width × height 0.95 × 0.83 × 0.3 0.95 × 0.83 × 0.3 0.95 × 0.83 × 0.3 inch

4 Detailed Description

The following sections provide a detailed description of the EVM.

Detailed Description

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4.1 Schematics

By default, the EVM is configured for drive pulse outputs, 18 V to turn ON, and –4 V to turn OFF, when a 3.3-V supply voltage is applied to the

input. Different settings are possible, described as follows. The configuration procedure is described based on the schematic shown in Figure 3.

Figure 3. UCC5390SCDEVM-010 Electrical Schematic

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Detailed Description

SLLU282A–December 2017–Revised February 2018

UCC5390SCD With Isolated Bias Supply

4.2 Driver Circuit Description

The supply voltage and input signals for driver U1 and bias supply U2 are applied through header J1.

Capacitors C3, C7, and C8 are located as close as possible to the VCC1 and GND1 terminals of U1 and

U2, to minimize EMI while operating as part of high dv/dt and di/dt power system. Resistors R2 and R3

and capacitors C1 and C2 provide additional filtering to protect input signals. These filters are optional and

may not be used in the systems where noise is limited. The secondary side noise decoupling is provided

by capacitors C2, C6, C9, C10, and C11. Split outputs of the driver U1 through gate resistors R1 and R4

are connected to FETs Q1 and Q2. These FETs are not populated on the board and their through hole

footprints are used to solder the board for evaluation on a system level, as it is shown in Figure 5. On this

board, the gate resistors have been selected at 1 Ω. However, as was described in Section 4.1, gate

resistor values determine switching rise and fall time with the power losses inside the driver IC, therefore

their values can be changed for specific requirements. Capacitor C5 can be used to estimate drive current

capability by measuring rise and fall time using the board separately. It is not populated on boards

intended to be used in a power system.

4.3 FET Recommendation

This board can be used with both IGBT and MOSFET-based power systems. FET selection does not

impact the board maximum power. The UCC5390S device limits the power dissipated by the board.

4.4 Bias Supply Circuit and Setting Description

By default, the bias supply outputs are set for 18 V turn ON voltage and –4V turn OFF voltage. The output

split rail is provided by Zener diode D5, resistor R5, and capacitors C6 and C11, with jumpers R7 and R6

removed. If a different turn OFF voltage is needed, a proper voltage-rated Zener diode and resistor can be

selected. If a split rail is not needed, then jumper R7 must be placed on the board and resistor R5 can be

removed. This will reduce overall power consumption initially dissipated inside resistor R5 and Zener

diode D5. Another bias supply option is possible by configuring the rectifier circuit as center-tapped or

bridge. Bridge configuration is provided by removing jumper R6. In this case, for the same input voltage

VCC, the output bias voltage is doubled versus the center-tapped rectifier. For the center-tapped rectifier,

the diodes D1 and D3 must be removed, and jumper R6 placed onboard. Table 3 lists possible

combinations of bias voltages, depending on nominal input voltage and rectifier configurations. These

voltages obviously depend on the transformer turn ratio. For this board, a transformer, 750342879, from

Würth-Midcom with a turn ratio 1:3.5 has been selected.

Table 3. Bias Voltage Configurations

Configuration Modification Input (V) Output (V)

Center-tapped, single

output Remove D1, D3, R5; place R7 and

R6 3.6 11

5 17

Bridge, single output Remove R5 and R6; place D1, D3,

R7 3.3 22

5 34

Center-tapped, split output Remove D1, D3, R7; place R5 and

R6 3.6 +7/–4

5 +13/-4

Bridge, split output Remove R7 and R6; place D1, D3,

R5 3.3 +18/-4

5 +30/–4

Test Summary

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5 Test Summary

5.1 Definitions

This test procedure details how to configure the test setup and capture key waveforms of the

UCC5390SCDEVM-010 boards when they operate in power system as part of a high voltage buck

converter.

5.2 Before You Begin

The following warnings and cautions are noted for the safety of anyone using or working close to the

UCC53x0 EVM. Observe all safety precautions.

CAUTION:

Caution! Warning: Hot surface contact may cause burns. Do not touch.

HOT SURFACE:

Precautions when operating.

HIGH VOLTAGE:

Danger: High voltage! The UCC53x0 device has an isolation boundary, but does not have safety

rated reinforced isolation. If you apply high voltage to this board, all terminals should be

considered high voltage. Electric shock is possible when connecting the board to live wire.

The board should be handled with care by a professional. For safety, TI highly recommends use

of isolated test equipment with overvoltage and overcurrent protection.

CAUTION

❏Do not leave the EVM unattended while powered.

❏All high voltage, high temperature, and hazard safety rules, applied to the

power system where these EVMs are embedded for bench evaluation, must

be strictly followed.

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Test Summary

SLLU282A–December 2017–Revised February 2018

UCC5390SCD With Isolated Bias Supply

5.3 Equipment

5.3.1 Power Supplies

TI recommends the following or similar DC power supplies for tests:

• At least up to 6-V and 1-A power supply for powering the EVM, for example: BK Precision, series 1715

• At least up to 1000-V and 1-A power supply for powering the power stage at the system level

evaluation, for example: Glassman FL1500 1.0

5.3.2 Function Generator

One 2-channel function generator over 20 MHz, for example: Tektronix AFG3102

5.3.3 BNC Feed-Thru Terminator

Two 50-ΩBNC male to female feed-thru terminators DC to 1 GHz, for example: Tektronix 011-0049-02

5.3.4 Oscilloscope

Oscilloscope 500-MHz or higher with four channels, for example: Tektronix DPO7104

5.3.5 Oscilloscope Probes

• At least 500-MHz bandwidth passive voltage probe, for example: Tektronix P6139A

• Two, at least 200-MHz bandwidth, 1000-V common mode differential voltage probes, for example:

Tektronix THDP020

• At least 50-MHz bandwidth current sense probe, for example: Tektronix TCP202

5.3.6 Digital Multi-Meters

Two digital multi-meters for evaluation of the EVM alone, and four digital multi-meters for evaluation on the

system level with a buck converter: for example Fluke 187

5.3.7 Electronic Load

Electronic load for system-level evaluation up to 500-V and 800-W, for example Kikusui PLZ603WH

5.3.8 Function Generator Settings

lists the 2-channel function generator settings.

Table 4. Two-Channel Function Generator Settings

Output Mode Frequency Width Delay High Low Output

Impedance Termination

Channel A Pulse 100 KHz 4.5 µs 0 ns 3 V 0 V 50 ΩFeed-thru 50

Ω

Channel B 5 µs

Test Summary

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5.3.9 Initial Oscilloscope Settings

Table 5 lists the initial oscilloscope settings. Because various bandwidth probes are used, it is

recommended to de-skew all channels to minimize delay differences.

Table 5. Initial Oscilloscope Settings

Output Bandwidth Probe Coupling Vertical Scale Horizontal

Scale Measured

Waveforms

Channel 1 ≥50 MHz TCP202 DC 2 A/div 2 µs/div Inductor current

Channel 2 ≥200 MHz THDP020 DC 10 V/div 2 µs/div Vgs, upper FET

Channel 3 ≥200 MHz THDP020 DC 200 V/div 2 µs/div Vds, lower FET

Channel 4 ≥500 MHz P6139A DC 10 V/div 2 µs/div Vgs, lower FET

5.3.10 Bench Setup

This EVM is designed to ensure easy and close connection to the power stage FET or IGBT in the TO-

220 or TO-247 package. Figure 4 shows an example of how the drive board can be attached and soldered

directly to the power FET terminals.

Figure 4. Soldering UCC5390SCDEVM-010 Board for System Level Evaluation

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