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TMS570LS0432, TMS570LS0332

SPNS186B –OCTOBER 2012–REVISED JUNE 2015

TMS570LS0x32 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1 Features

• High-Performance Automotive-Grade • Multiple Communication Interfaces

Microcontroller for Safety-Critical Applications – Two CAN Controllers (DCANs)

– Dual CPUs Running in Lockstep • DCAN1 - 32 Mailboxes With Parity

– ECC on Flash and RAM Interfaces Protection

– Built-In Self-Test for CPU and On-Chip RAMs • DCAN2 - 16 Mailboxes With Parity

Protection

– Error Signaling Module With Error Pin • Compliant to CAN Protocol Version 2.0B

– Voltage and Clock Monitoring – Multibuffered Serial Peripheral Interface

• ARM®Cortex®-R4 32-Bit RISC CPU (MibSPI) Module

– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline • 128 Words With Parity Protection

– 8-Region Memory Protection Unit (MPU) – Two Standard Serial Peripheral Interface (SPI)

– Open Architecture With Third-Party Support Modules

• Operating Conditions – UART (SCI) Interface With Local Interconnect

– 80-MHz System Clock Network (LIN 2.1) Interface Support

– Core Supply Voltage (VCC): 1.2-V Nominal • Next Generation High-End Timer (N2HET) Module

– I/O Supply Voltage (VCCIO): 3.3-V Nominal – Up to 19 Programmable Pins

– ADC Supply Voltage (VCCAD): 3.3-V Nominal – 128-Word Instruction RAM With Parity

• Integrated Memory Protection

– Up to 384KB of Program Flash With ECC – Includes Hardware Angle Generator

– 32KB of RAM With ECC – Dedicated High-End Timer Transfer Unit (HTU)

– 16KB of Flash for Emulated EEPROM With With MPU

ECC • Enhanced Quadrature Encoder Pulse (eQEP)

• Hercules™ Common Platform Architecture Module

– Consistent Memory Map Across Family – Motor Position Encoder Interface

– Real-Time Interrupt (RTI) Timer (OS Timer) • 12-Bit Multibuffered Analog-to-Digital Converter

– 96-Channel Vectored Interrupt Module (VIM) (ADC) Module

– 2-Channel Cyclic Redundancy Checker (CRC) – 16 Channels

• Frequency-Modulated Phase-Locked Loop – 64 Result Buffers With Parity Protection

(FMPLL) With Built-In Slip Detector • Up to 45 General-Purpose Input/Output (GPIO)

• IEEE 1149.1 JTAG Boundary Scan and ARM Pins

CoreSight™ Components – 8 Dedicated Interrupt-Capable GPIO Pins

• Advanced JTAG Security Module (AJSM) • Package

– 100-Pin Quad Flatpack (PZ) [Green]

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS570LS0432, TMS570LS0332

SPNS186B –OCTOBER 2012–REVISED JUNE 2015

www.ti.com

1.2 Applications

• Braking Systems (ABS and ESC) • Active Driver Assistance Systems

• Electric Power Steering (EPS) • Aerospace and Avionics

• Electric Pump Control • Railway Communications

• Battery-Management Systems • Off-road Vehicles

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SPNS186B –OCTOBER 2012–REVISED JUNE 2015

1.3 Description

The TMS570LS0432/0332 device is a high-performance automotive-grade microcontroller for safety

systems. The safety architecture includes dual CPUs in lockstep, CPU and Memory BIST logic, ECC on

both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral

I/Os.

The TMS570LS0432/0332 device integrates the ARM Cortex-R4 CPU. The CPU offers an efficient

1.66 DMIPS/MHz, and has configurations that can run up to 80 MHz, providing up to 132 DMIPS. The

device supports the big-endian (BE32) format.

The TMS570LS0432/0332 device has 384KB and 256KB of integrated flash (respectively) and 32KB of

data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The

flash memory on this device is a nonvolatile, electrically erasable, and programmable memory

implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (the same

level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates

with a system clock frequency of 80 MHz. The SRAM supports single-cycle read and write accesses in

byte, halfword, word, and double-word modes throughout the supported frequency range.

The TMS570LS0432/0332 device features peripherals for real-time control-based applications, including a

Next Generation High-End Timer (N2HET) timing coprocessor with up to 19 I/O terminals and a 12-bit

Analog-to-Digital Converter (ADC) supporting 16 inputs in the 100-pin package.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a small instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,

capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer

Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.

A Memory Protection Unit (MPU) is built into the HTU.

The Enhanced Quadrature Encoder Pulse (eQEP) module is used for direct interface with a linear or

rotary incremental encoder to get position, direction, and speed information from a rotating machine as

used in high-performance motion and position-control systems.

The device has a 12-bit-resolution MibADC with 16 channels and 64 words of parity-protected buffer RAM.

The MibADC channels can be converted individually or can be grouped by software for sequential

conversion sequences. There are three separate groupings. Each sequence can be converted once when

triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when

compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: one MibSPI, two SPIs, one UART/LIN, and two

DCANs. The SPI provides a convenient method of serial high-speed communications between similar

shift-register type devices. The UART/LIN supports the Local Interconnect standard 2.1 and can be used

as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports

the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that

efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The

DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and

industrial applications) that require reliable serial communication or multiplexed wiring.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external

frequency reference to a higher frequency for internal use. The FMPLL provides one of the five possible

clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the

available clock sources and the device clock domains.

The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous

external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral

interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of

the device operating frequency.

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TMS570LS0432, TMS570LS0332

SPNS186B –OCTOBER 2012–REVISED JUNE 2015

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The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is

generated or the external nERROR pin is toggled when a fault is detected. The nERROR pin can be

monitored externally as an indicator of a fault condition in the microcontroller.

The I/O Multiplexing and Control Module (IOMM) allows the configuration of the input/output pins to

support alternate functions. See Table 4-17 for a list of the pins that support multiple functions on this

device.

With integrated safety features and a wide choice of communication and control peripherals, the

TMS570LS0432/0332 device is an ideal solution for real-time control applications with safety-critical

requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE

TMS570LS0432PZ LQFP (100) 14.00 mm × 14.00 mm

TMS570LS0332PZ LQFP (100) 14.00 mm × 14.00 mm

(1) For more information, see Section 9,Mechanical Packaging and Orderable Information.

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ESM

Flash

with ECC

384KB(A)

CRC

2 Channel

Peripheral

Bridge

PCR

N2HET

128 Words

with Parity

SYS

GIO

LIN

MiBSPI1

8 Transfer

Groups

128 Buffers

with Parity

DCAN1

32 Messages

with Parity

nTRST

TMS

TCK

TDI

TDO

nRST

nPORRST

TEST

N2HET[31:28, 26, 24:22, 20:16,

14, 12, 10, 8, 6, 4, 2, 0]

GIOA[7:0]/INT[7:0]

LINRX

LINTX

MIBSPI1SIMO

MIBSPI1SOMI

MIBSPI1CLK

MIBSPI1nCS[3:0]

CAN1RX

CAN1TX

FLTP1

ECLK

DCAN2

16 Messages

with Parity

CAN2RX

CAN2TX

VIM

96 Channel

with Parity

CCM-R4

RTCK

nERROR

MIBSPI1nENA

FLTP2

with ECC

RAM

32KB

Slave I/F

RTI

MiBADC

64 Words

with Parity

ADIN[21, 20, 17, 16, 11:0]

VCCAD / ADREFHI

VSSAD / ADREFLO

ADEVT

SPI2

SPI2SIMO

SPI2SOMI

SPI2CLK

SPI2nCS[0]

STC

LBIST

Debug

Gasket

SCR

DAP

with

ICEPick

HTU

2 Regions

8 DCP

with MPU

BRIDGE

Cortex-R4

with MPU

8 regions

16KB

Flash for

EEPROM

w/ECC

VCCP

Cortex-R4

with MPU

8 regions

OSCIN

OSCOUT

VCCPLL

VSSPLL

Kelvin_GND

OSC

PLL

Clock

Monitor

AJSM

eQEP

DCC

IOMM

eQEPA

eQEPB

eQEPS

eQEPI

SPI3

SPI3SIMO

SPI3SOMI

SPI3CLK

SPI3nCS[3:0]

SPI3nENA

TMS570LS0432, TMS570LS0332

www.ti.com

SPNS186B –OCTOBER 2012–REVISED JUNE 2015

1.4 Functional Block Diagram

Figure 1-1 shows a functional block diagram of the device.

A. The TMS570LS0332 device only supports 256KB Flash with ECC.

Figure 1-1. Functional Block Diagram

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TMS570LS0432, TMS570LS0332

SPNS186B –OCTOBER 2012–REVISED JUNE 2015

www.ti.com

Table of Contents

1 Device Overview ......................................... 16.9 Flash Memory ....................................... 50

6.10 Flash Program and Erase Timings for Program

1.1 Features .............................................. 1Flash ................................................ 52

1.2 Applications........................................... 26.11 Flash Program and Erase Timings for Data Flash.. 52

1.3 Description............................................ 36.12 Tightly Coupled RAM Interface Module............. 53

1.4 Functional Block Diagram ............................ 56.13 Parity Protection for Accesses to peripheral RAMs.53

2 Revision History ......................................... 76.14 On-Chip SRAM Initialization and Testing ........... 54

3 Device Comparison ..................................... 86.15 Vectored Interrupt Manager......................... 56

4 Terminal Configuration and Functions ............. 96.16 Real-Time Interrupt Module ......................... 58

4.1 PZ QFP Package Pinout (100-Pin)................... 96.17 Error Signaling Module.............................. 59

4.2 Terminal Functions ................................. 10 6.18 Reset / Abort / Error Sources ....................... 63

4.3 Output Multiplexing and Control..................... 16 6.19 Digital Windowed Watchdog ........................ 64

4.4 Special Multiplexed Options......................... 17 6.20 Debug Subsystem................................... 65

5 Specifications .......................................... 18 7 Peripheral Information and Electrical

5.1 Absolute Maximum Ratings......................... 18 Specifications........................................... 70

5.2 ESD Ratings ........................................ 18 7.1 Peripheral Legend................................... 70

5.3 Power-On Hours (POH)............................. 18 7.2 Multibuffered 12-Bit Analog-to-Digital Converter.... 70

5.4 Recommended Operating Conditions............... 19 7.3 General-Purpose Input/Output ...................... 78

5.5 Switching Characteristics Over Recommended 7.4 Enhanced High-End Timer (N2HET)................ 79

Operating Conditions for Clock Domains ........... 19 7.5 Controller Area Network (DCAN).................... 82

5.6 Wait States Required ............................... 20 7.6 Local Interconnect Network Interface (LIN) ......... 83

5.7 Power Consumption ................................ 21 7.7 Multibuffered / Standard Serial Peripheral Interface 84

5.8 Thermal Resistance Characteristics for PZ......... 22 7.8 Enhanced Quadrature Encoder (eQEP) ............ 94

5.9 Input/Output Electrical Characteristics.............. 22 8 Device and Documentation Support ............... 96

5.10 Output Buffer Drive Strengths ...................... 23 8.1 Device Support...................................... 96

5.11 Input Timings........................................ 24 8.2 Documentation Support ............................. 99

5.12 Output Timings...................................... 25 8.3 Related Links........................................ 99

6 System Information and Electrical

Specifications........................................... 27 8.4 Community Resources.............................. 99

6.1 Voltage Monitor Characteristics..................... 27 8.5 Trademarks.......................................... 99

6.2 Power Sequencing and Power-On Reset........... 28 8.6 Electrostatic Discharge Caution..................... 99

6.3 Warm Reset (nRST)................................. 30 8.7 Glossary............................................. 99

6.4 ARM Cortex-R4 CPU Information................... 31 8.8 Device Identification Code Register ............... 100

6.5 Clocks ............................................... 35 8.9 Die Identification Registers ....................... 100

6.6 Clock Monitoring .................................... 41 8.10 Module Certifications............................... 101

6.7 Glitch Filters......................................... 43 9 Mechanical Packaging and Orderable

Addendum.............................................. 106

6.8 Device Memory Map ................................ 44 9.1 Packaging Information ............................. 106

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SPNS186B –OCTOBER 2012–REVISED JUNE 2015

2 Revision History

Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the

TMS570LS0432 devices, which are now in the production data (PD) stage of development have been

incorporated.

Changes from April 30, 2014 to June 30, 2015 (from A Revision (April 2014) to B Revision) Page

• Updated/Changed section title to "Device Overview" ........................................................................... 1

• Added Section 1.3 (Description): Added paragraph describing IOMM ....................................................... 4

•Section 1.3 (Description): Added the Device Information table................................................................. 4

•Figure 1-1 (Functional Block Diagram): Added flash footnote.................................................................. 5

• Added Section 3,Device Comparison ............................................................................................. 8

•Section 5 (Specifications): Updated/Changed section title .................................................................... 18

•Section 5.2 (ESD Ratings): Added section ...................................................................................... 18

•Section 5.3 (Power-On Hours (POH)): Added table (new) .................................................................... 18

•Table 5-4 (Selectable 8mA/2mA Control): Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI

pin in footnote........................................................................................................................ 23

•Section 6.4.1 (Summary of ARM Cortex-R4 CPU Features): Added Quantity of Breakpoints and Watchpoints ...... 31

•Section 6.20.3 (JTAG Identification Code): Added a table showing JTAG ID code for each silicon revision........... 65

•Table 7-7 (MibADC Operating Characteristics ): Added missing footnote for ZSET 10-/12-bit modes.................... 74

•Section 7.7.1 (Features [MibSPI]): Updated/Changed size of SPI baud clock generator from "8-bit" to "11-bit"....... 84

•Section 8 (Device and Documentation Support): Updated/Changed section outline structure ........................... 96

•Section 8.1 (Device Support): Added section (new)............................................................................ 96

•Section 8.1.1 (Development Support, Hardware Development Tools): Updated/Changed the JTAG-based

emulators specified ................................................................................................................. 96

•Section 8.1.2 (Device Nomenclature): Updated/Changed section title....................................................... 97

•Section 8.1.2: Deleted the support tool development (TMDX/TMDS) references .......................................... 97

•Section 8.8 (Device Identification Code Register): Added silicon revision B device identification code ............... 100

•Section 8.9 (Die Identification Registers): Updated/Changed the DIEIDL and DIEIDH to point to the original

registers at location 0xFFFFFF7C and 0xFFFFFF80 ........................................................................ 100

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SPNS186B –OCTOBER 2012–REVISED JUNE 2015

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3 Device Comparison

Table 3-1 lists the features of the TMS570LS0432/0332 devices.

Table 3-1. TMS570LS0432/0332 Device Comparison(1)(2)

FEATURES DEVICES

Generic Part TMS570LS1227ZWT(3) TMS570LS0714ZWT TMS570LS0714PGE TMS570LS0714PZ TMS570LS0432PZ(3) TMS570LS0332PZ TMS570LS0232PZ

Number

Package 337 BGA 337 BGA 144 QFP 100 QFP 100 QFP 100 QFP 100 QFP

CPU ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4 ARM Cortex-R4 ARM Cortex-R4

Frequency (MHz) 180 180 160 100 80 80 80

Flash (KB) 1280 768 768 768 384 256 128

RAM (KB) 192 128 128 128 32 32 32

Data Flash 64 64 64 64 16 16 16

[EEPROM] (KB)

EMAC 10/100 – – – – – –

FlexRay 2-ch – – – – – –

CAN 3 3 3 2 2 2 2

MibADC 2 (24ch) 2 (24ch) 2 (24ch) 2 (16ch) 1 (16ch) 1 (16ch) 1 (16ch)

12-bit (Ch)

N2HET (Ch) 2 (44) 2 (44) 2 (40) 2 (21) 1 (19) 1 (19) 1 (19)

ePWM Channels 14 14 14 8 – – –

eCAP Channels 6 6 6 4 0 0 0

eQEP Channels 2 2 2 1 1 1 1

MibSPI (CS) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (5 + 6 + 4) 2 (5 + 1) 1 (4) 1 (4) 1 (4)

SPI (CS) 2 (2 + 1) 2 (2 + 1) 1 (1) 1 (1) 2 2 2

SCI (LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 1 (with LIN) 1 (with LIN) 1 (with LIN) 1 (with LIN)

I2C 1 1 1 – – – –

101 (with 16 101 (with 16 64 (with 10 45 (with 9 45 (with 8 45 (with 9 45 (with 8

GPIO (INT)(4) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable)

EMIF 16-bit data – – – – – –

ETM (Trace) – – – – – – –

RTP/DMM – – – – – – –

Operating –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC

Temperature

Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V

I/O Supply (V) 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V

(1) For additional device variants, see www.ti.com/tms570

(2) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the

same time.

(3) Superset device

(4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral.

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MIBSPI1nCS[1]

VCCP

LINRX

VCCIO

ECLK

RTCK

N2HET[6]

MIBSPI1nCS[2]

VCCIO

VSS

VCC

nPORRST

VCC

VSS

SPI3nENA

ADIN[21]

TCK

SPI3nCS[0]

MIBSPI1nCS[3]

ADIN[0]

ADIN[7]

ADIN[20]

VSSAD/ADREFLO

ADIN[9]

VCCAD/ADREFHI

ADIN[1]

ADIN[10]

VSS

VCC

CAN2RX

CAN2TX

VCC

VSS

nERROR

nRST

TDO

TDI

nTRST

VSS

LINTX

SPI3CLK

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[5]

ADIN[6]

ADEVT

VSS

CAN1TX

CAN1RX

MIBSPI1SOMI

MIBSPI1C LK

MIBSPI1nENA

SPI2SOMI

SPI2SIMO

SPI2CLK

MIBSPI1nCS[0]

TMS

VCC

MIBSPI1SIMO

VCCIO

GIOA[3]

VSS

VCCIO

GIOA[1]

TEST

SPI2nCS[0]

GIOA[7]

VSS

KELVIN_GN D

OSCIN

VC C

GIOA[6]

GIOA[5]

GIOA[2]

FLTP2

FLTP 1

GIOA[0]

GIOA[4]

OSCOUT

100

VSS

VC C

VSS

SPI3SOMI

SPI3SIMO

ADIN[16]

ADIN[17]

ADIN[11]

ADIN[8]

N2HET[4]

N2HET[2]

N2HET[0]

N2HET[022]

N2HET[024]

N2HET[8]

N2HET[10]

N2HET[8]

N2HET[14]

N2HET[12]

N2HET[16]

N2HET[18]

TMS570LS0432, TMS570LS0332

www.ti.com

SPNS186B –OCTOBER 2012–REVISED JUNE 2015

4 Terminal Configuration and Functions

4.1 PZ QFP Package Pinout (100-Pin)

Figure 4-1 shows the 100-pin PZ QFP package pinout.

Figure 4-1. PZ QFP Package Pinout (100-Pin)

Note: Pins can have multiplexed functions. Only the default function is depicted in Figure 4-1.

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SPNS186B –OCTOBER 2012–REVISED JUNE 2015

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4.2 Terminal Functions

Table 4-1 through Table 4-16 identify the external signal names, the associated pin numbers along with

the mechanical package designator, the pin type (Input, Output, I/O, Power, or Ground), whether the pin

has any internal pullup/pulldown, whether the pin can be configured as a GPIO, and a functional pin

description.

NOTE

In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to

the terminal while nPORRST is low and immediately after nPORRST goes High. The default

pull direction may change when software configures the pin for an alternate function. The

"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given

terminal by the IOMM control registers.

All I/O signals except nRST are configured as inputs while nPORRST is low and

immediately after nPORRST goes High. While nPORRST is low, the input buffers

are disabled, and the output buffers are disabled with the default pulls enabled.

All output-only signals have the output buffer disabled and the default pull enabled

while nPORRST is low, and are configured as outputs with the pulls disabled

immediately after nPORRST goes High.

4.2.1 High-End Timer (N2HET)

Table 4-1. High-End Timer (N2HET)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION

TYPE PULL

SIGNAL NAME 100 STATE

N2HET[0] 19 I/O Pulldown Programmable, Timer input capture or output compare. The

20 µA N2HET applicable terminals can be programmed

N2HET[2] 22 as general-purpose input/output (GPIO).

N2HET[4] 25 Each terminal has a suppression filter with a

programmable duration.

N2HET[6] 26

N2HET[8] 74

N2HET[10] 83

N2HET[12] 89

N2HET[14] 90

N2HET[16] 97

MIBSPI1nCS[1]/EQEPS/ 93

N2HET[17]

N2HET[18] 98

MIBSPI1nCS[2]/N2HET[20]/ 27

N2HET[19]

MIBSPI1nCS[2]/N2HET[20]/ 27

N2HET[19]

N2HET[22] 11

N2HET[24] 64

MIBSPI1nCS[3]/N2HET[26] 39

ADEVT/N2HET[28] 58

GIOA[7]/N2HET[29] 18

MIBSPI1nENA/N2HET[23]/ 68

N2HET[30]

GIOA[6]/SPI2nCS[1]/N2HET[31] 12

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