Texas Instruments CDCE906 Bedienungsanleitung

CDCE906/CDCE706 PerformanceEvaluation Module

User's Guide

August 2007 High Performance Analog/CDC

SCAU016B

2 SCAU016B – August 2006 – Revised August 2007Submit Documentation Feedback

Contents

1 Introduction ................................................................................................................ 52 Quick Start ................................................................................................................. 83 EVM Hardware ............................................................................................................ 93.1 Board View and Connector Location .......................................................................... 93.2 Hardware Configuration ......................................................................................... 94 TI Pro-Clock™ ........................................................................................................... 114.1 CDCE906-706 SMBus Interface .............................................................................. 114.2 CDCE906-706 Programming Assistant ...................................................................... 124.3 Tutorial ........................................................................................................... 144.4 Software Installation ............................................................................................ 155 FAQ ......................................................................................................................... 166 Parts List .................................................................................................................. 167 Board Layout and Schematic ...................................................................................... 18

Important Notices ............................................................................................................... 25

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List of Figures

1 CDCE906/CDCE706 Functional Block Diagram ......................................................................... 62 CDCE906/CDCE706 Default Setup ....................................................................................... 83 Board View ................................................................................................................... 94 CDCE906-706 SMBus Interface ......................................................................................... 115 Programming Assistant .................................................................................................... 136 Top Silkscreen .............................................................................................................. 187 Top Side ..................................................................................................................... 198 Ground ....................................................................................................................... 209 Power ........................................................................................................................ 2110 Bottom Silkscreen .......................................................................................................... 2211 Schematic - Page 1 ........................................................................................................ 2312 Schematic - Page 2 ........................................................................................................ 24

List of Tables

1 Parts List .................................................................................................................... 16

4List of Figures SCAU016B – August 2006 – Revised August 2007Submit Documentation Feedback

1 Introduction

User's GuideSCAU016B – August 2006 – Revised August 2007

CDCE906/CDCE706 Performance Evaluation Module

This user's guide explains how to use the CDCE906/CDCE706 performance evaluation module andprovides guidelines to build a customer's own systems. The device is soldered on the board to supportperformance measurements. The device is preprogrammed (Default Setting), but can be reprogrammedvia the parallel port to meet the customer application. There is another EVM with socket available for thepurpose of sample programming. The list below shows the four devices, which can be evaluated with theCDCE906/CDCE706 Performance Evaluation Module

- CDCE706 (EEPROM, f

max

= 300 MHz, industrial temperature range)

- CDCE906 (EEPROM, f

max

= 167 MHz, commercial temperature range)

- CDC706 (ROM, f

max

= 300 MHz, industrial temperature range)

- CDC906 (ROM, f

max

= 167 MHz, commercial temperature range)

The performance of the CDCE906 and the CDCE706 is equal, but the CDCE906 has a limited outputfrequency and temperature range for operating. Because of this, the CDCE706 is used on this board forevaluation purposes. This EVM can also be used to evaluate the generic ROM versionsCDC906/CDC706, because the functionality and performance is equal to the EEPROM versionCDCE906/CDCE706, except the EEPROM functionality.

If you need assistance with this device, email: [email protected]

The CDCE906/CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divideravailable today. Despite its small physical outlines, the CDCE906/CDCE706 is the most flexible. It has thecapability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, a differential input clock, or a single crystal. Theappropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for eachPLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. ThePLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable outputswitching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider(1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from e.g., a 27-MHz reference inputfrequency.

The CDCE906/CDCE706 includes three PLLs of those one supports SSC (spread-spectrum clocking).PLL1, PLL2, and PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppmapplications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a proven method toeffectively reduce the energy for the selected frequency range. The electro-magnetic interference (EMI)will be significantly reduced. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will beautomatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

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CLK_IN0

CLK_IN1

Factory Prg.

PLL1

MUX

prg. 9 Bit

Divider M

prg. 9 Bit

Divider M

MUX

prg. 9 Bit

Divider M

PLL3

PFD

Filter

VCO

PLL2

w/ SSC

PFD

Filter

VCO

SSC

prg. 12 Bit

Divider N

prg. 12 Bit

Divider N

prg. 12 Bit

Divider N

SO/AO/CLK_SEL

S1/A1

SCLOCK

Output Switch Matrix

PLL Bypass

CMOS

EEPROM

LOGIC

PFD

Filter

VCO

SDATA

2 LVCMOS

Differential

Input

VCC GND VCCOUT1

GND VCCOUT2

Crystal or

Clock Input

14 pF

5x 6 Programmable Switch A

6 x Programmable 7-Bit Divider P0, P1, P2, P3, P4, P5, and Inversion Logic

6 x 6 Programmable Switch B

Introduction

The device supports non-volatile EEPROM programming for easy customized applications. It ispre-programmed with a factory default configuration (see Figure 2 ) and can be re-programmed to adifferent application configuration before it goes onto the PCB or re-programmed by in-systemprogramming. A different register setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the mostdemanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906/CDCE706 has three power supply pins, VCC, VCCOUT1, and VCCOUT2. VCC is thepower supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 arethe power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 suppliesthe outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. The output works even at1.7V VCCOUT. However, some limitations apply at VCCOUT below 2.3V.

The CDCE906/CDCE706 is characterized for operation from 0 °C to 70 °C/–40 °C to 85 °C.

Figure 1. CDCE906/CDCE706 Functional Block Diagram

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Introduction

Related Documentation From Texas Instruments•CDCE906, Programmable 3-PLL Clock Synthesizer/Multiplier/Divider data sheet (SCAS814 )

•CDCE706, Programmable 3-PLL Clock Synthesizer/Multiplier/Divider data sheet (SCAS815 )

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2 Quick Start

SO/AO/CLK_SEL

S1/A1

SCLOCK

Output Switch Matrix

27 MHz

SDATA

f = 216 MHz

VCO1

f = 250 MHz

VCO2

f = 225.792 MHz

VCO3

CLK_IN0

CLK_IN1

27-MHz

Crystal

14 pF

27 MHz

P2-Div

P3-Div

P4-Div

P5-Div

CMOS

Divider M

375

Divider N

250

Divider N

3136

SSC-OFF

PLL1

PLL3

PLL2

w/ SSC

2 LVCMOS

Differential

Input

EEPROM

LOGIC

SMBUS

LOGIC

PFD

Filter

VCO

PFD

Filter

VCO

PFD

Filter

VCO

Divider M

Divider N

MUX

P0-Div

P1-Div

MUX

Quick Start

The device is already preprogrammed and provides a 27MHz clock at every output. A 27MHz crystal isused as reference.

To start the measurements the following actions are required:•Connect 3.3 V to P1, P2, P3, and GND to P4.•Connect one of the six outputs (Y0–Y5) to an oscilloscope.•Connect the oscilloscope to the output that will be measured.

In the Default Setup, the clock input pins CLK_IN0 and CLK_IN1 are connected to a 27-MHz crystal. AllPLLs and all outputs are active and in non-inverting mode. S0, S1, and SSC comply according the defaultsetting described in byte 10 and byte 25 (see the data sheet) respectively.

See Figure 2 to view the CDCE906/CDCE706 default setup.

Figure 2. CDCE906/CDCE706 Default Setup

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3 EVM Hardware

3.1 Board View and Connector Location

GND (P4)

VCC (P3)

VCC Y0-Y1 (P2)

VCC Y2-Y5 (P1)

Parallel Port

(J18)

CDCE706

SMA connector for Y0 – Y5

connector for single/differential ended input clock

(J3, J6)

27 MHz Crystal

TSX-3225 (Y1)

S1 S0

SN74LV125

J17

3.2 Hardware Configuration

3.2.1 Power Supply (P1, P2, P3, P4)

3.2.2 Onboard Jumper (J12 and J10)

EVM Hardware

Figure 3. Board View

This section describes the board configuration using on-board jumpers and solder-bridges as well as theSMBUS interface.

Use a stabilized external power supply for the EVM board.•Supply 3.3 V ±0.3 V on P3 for chip operation.•Supply 2.3 V – 3.6 V on P2 to supply the outputs Y0 and Y1.•Supply 2.3 V – 3.6 V on P1 to supply the outputs Y2–Y5.•Connect GND to P4.

WARNINGNever supply more than 3.6 V on P1, P2, or P3.

Use Jumper J10 to set the user programmable control input S0 to low or high.

Use Jumper J12 to set the user programmable control input S1 to low or high.

Default setting: J12 and J10 are not used.

Note: S0 and S1 are logic high due to their internal pull-up resistors if J10 and J12 are not used.

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3.2.3 Programming Interfaces (J18, J17)

3.2.4 Flexible Crystal, Differential or LVCMOS Input (J3, J6)

3.2.5 LVCMOS Outputs (Y0 –Y5)

EVM Hardware

To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Itfollows the SMBus specification Version 2.0, which is based upon the principals of operation of I

C. Moredetails of the SMBus specification can be found at http://www.smbus.org .

Through the SMBus, various device functions, such as individual clock output buffers, can be individuallyenabled or disabled. The registers associated with the SMBus data interface initialize to their defaultsetting, written in the EEPROM, upon power-up and therefore using this interface is optional. Clock deviceregister changes are normally made upon system initialization, if any are required. There are two ways toprogram the device externally.•Connect the parallel port cable to PC and EVM parallel port. This needs the TI Pro Clock™ Software(see section 4).•By external pattern generator connected to J17 (it is not possible to detect an acknowledge at J17)

Note: The shield of the parallel cable should be connected to both cable plugs.

The CDCE906/CDCE706 can use a crystal, a differential clock, or a single-ended clock as reference. Thedefault setting is a 27MHz crystal.

For a differential or a single-ended clock R2, R4, R5, and R6 must be assembled with 100 Ω, pin 2 and 3of J4 and pin 1 and pin 2 of J5 must be shorted. This will assure correct biasing and results in a 50 Ωparallel termination at the CDCE906/CDCE706 input. The assembly of R3 and R7 is not necessary. Asingle-ended clock can then be applied to J3 or J6. A differential-ended clock must be applied to J3 andJ6.

Default settings: 27-MHz Crystal

The CDCE906/CDCE706 drives up to six LVCMOS outputs. All outputs are ac-coupled and have a 0- Ωseries termination resistor. The device output’s trace impedance is 50 Ωand all traces are matched inlength. The output has additional resistor and capacitor footprints to provide high flexibility for differentuser defined terminations. All traces have option for pull-up, pull-down resistors and on board dc-biasing.

There is no additional load on the EVM Default Setting. This provides the maximum possible swing to ascope, a spectrum analyzer, or another EVM with high impedance input, that is connected to theCDCE906/E706 performance EVM. However, the output load is too low if Y0–Y5 is connected directly to a50 Ωparallel termination. This results in a violation of the ac-parameters mentioned in the data sheet.

To maintain the ac-parameters by connecting 50 Ωto Y0–Y5 a voltage divider is needed to provide asufficient output load for the LVCMOS outputs. The following steps are necessary to create the voltagedivider:

•Replace R10, R15, R25, R30, R40, and R43 with 0 Ω.•Assemble R8, R12, R23, R26, R38, and R42 with 1 k Ω.•Assemble C7, C8, C9, C10, C11, and C12 with 950 Ω.•Assemble R17, R19, R34, R35, R46, and R47 with 10 pF.

The output voltage of Y0-Y5 will be divided by 20 in this configuration. The overall ac load to GND will be500 Ω//10 pF if the input impedance of the measurement equipment is 50 Ω.

Alternative R10, R15, R25, R30, R40, and R43 can be replaced with 450 Ωto provide 500 Ωto GND. Theoutput voltage of Y0–Y5 will be divided by 10, if the input impedance of the measurement equipment is 50Ω.

CDCE906/CDCE706 Performance Evaluation Module10 SCAU016B – August 2006 – Revised August 2007Submit Documentation Feedback

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