Texas Instruments DAC8554EVM Bedienungsanleitung

User's GuideSBAU121 – January 2006

DAC8554EVM User's Guide

This user’s guide describes the characteristics, operation and use of the DAC8554Evaluation Module (EVM). It covers all matters related to proper use and configurationof this EVM along with the devices that it supports. The physical printed circuit board(PCB) layout, schematic diagram and circuit descriptions are also included. For a moredetailed description of the DAC8554 , please refer to the product datasheet availablefrom the Texas Instruments web site at http://www.ti.com. Additional supportdocuments are listed in the section of this guide entitled Related Documentation fromTexas Instruments. Throughout this document, the acronym EVM and the phrasesevaluation module and demonstration board are synonymous with the DAC8554EVM.

Contents1 Overview ............................................................................................. 22 PCB Design and Performance .................................................................... 43 EVM Operation .................................................................................... 144 Schematic .......................................................................................... 20

List of Figures

1 DAC8554EVM Functional Block Diagram ....................................................... 32 DAC8554EVM PCB—Top Silkscreen Image ................................................... 53 DAC8554EVM PCB—Layer 1 (Top Signal Layer) ............................................. 54 DAC8554EVM PCB—Layer 2 (Ground Plane) ................................................. 65 DAC8554EVM PCB—Layer 3 (Power Plane) .................................................. 66 DAC8554EVM PCB—Layer 4 (Bottom Signal Layer) ......................................... 77 DAC8554EVM PCB—Bottom Silkscreen Image ............................................... 78 DAC8554EVM—Drill Drawing..................................................................... 89 INL and DNL Characterization Graph of DAC A ............................................... 910 INL and DNL Characterization Graph of DAC B .............................................. 1011 INL and DNL Characterization Graph of DAC C .............................................. 1112 INL and DNL Characterization Graph of DAC D .............................................. 12

List of Tables

1 DAC8554EVM Parts List ......................................................................... 132 Factory Default Jumper Settings ................................................................ 143 DAC Output Channel Mapping .................................................................. 154 Unity Gain Output Jumper Settings ............................................................. 165 Output Gain of 2 Jumper Settings .............................................................. 166 Capacitive Load Drive Output Jumper Settings ............................................... 177 Jumper Settings and Functions ................................................................. 17

LabVIEW is a trademark of National Instruments.All trademarks are the property of their respective owners.

SBAU121 – January 2006 DAC8554EVM User's Guide 1

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1 Overview

1.1 Features

1.2 Power Requirements

Overview

This section gives a general overview of the DAC8554EVM and describes some of the factors that mustbe considered when using this demonstration board.

The DAC8554EVM is a simple evaluation module designed for a quick and easy way to evaluate thefunctionality and performance of the high-resolution, quad-channel, serial input DAC8554 digital-to-analogconverter (DAC). This EVM features a serial interface to communicate with any host microprocessor or TIDSP-based system.

This subsection describes the power requirements for this device.

1.2.1 Supply Voltage

The DC power supply requirement for the digital section (V

) of this EVM is typically +5V connected tothe J5-1 terminal or via the J3-10 terminal (when plugged in with another EVM board or interface card)and is referenced to ground through the J5-2 and J3-5 terminals. The DC power supply requirements forthe analog section of this EVM are: V

and V

range from +15.75V to –15.75V (maximum), connectingthrough J1-3 and J1-1 respectively, or through terminals J3-1 and J3-2. The +5V

connects throughterminals J5-3 or J3-3, and the +3.3V

connects through terminal J3-8. All of the analog power suppliesare referenced to analog ground through terminals J1-2 and J3-6.

The analog power supply for the device under test, U1, can be powered by either +5V

or +3.3V

byselecting the proper position of jumper JMP7. This configuration allows the DAC8554 analog section tooperate from either supply power while the I/O and digital section are powered by +5V, V

The V

supply source is primarily used to provide the positive rail of the external output op amp, U2, thereference chip, U3 and the reference buffer, U4. The negative rail of the output op amp, U2, can beselected between V

and AGND via jumper JMP10. The external op amp is installed as an option toprovide output signal conditioning or to boost capacitive load drive, or for other desired output moderequirements.

CAUTIONTo avoid potential damage to the EVM board, be sure that the correctcables are connected to their respective terminals as labeled on the EVMboard. Stresses above the maximum listed voltage ratings may causepermanent damage to the device.

1.2.2 Reference Voltage

The +5V precision voltage reference is provided to supply the external voltage reference for the DACthrough the REF02 (U3) via jumper JMP8, by shorting pins 1 and 2. The reference voltage goes throughan adjustable 100k Ωpotentiometer, R15, in series with 20k Ω, R16, to allow the user to adjust thereference voltage to its desired settings. The voltage reference is then buffered through U4A as seen bythe device under test. The test points TP2, TP3 and TP4 are also provided, as well as J4-18 and J4-20, inorder to allow the user to connect another external reference source if the onboard reference circuit is notdesired. The external voltage reference should not exceed +5V DC.

The REF02 precision reference is powered by V

(+15V) through either terminal J1-3 or J3-1.

CAUTIONWhen applying an external voltage reference through TP2 or J4-20, makesure that it does not exceed +5V maximum. External voltage references inexcess of +5V can permanently damage the DAC8554 being tested (U1).

2DAC8554EVM User's Guide SBAU121 – January 2006

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1.3 EVM Basic Functions

JMP11

JMP12

JMP13

JMP14

External

Reference

Module

+5VA

VDD

+3.3VA

(J2A)

(J2B)

DAC Module

(J4A)

(J4B) 8 CH

(J1)

(J5)

(J3A)

(J3B)

4 CH

JMP15

JMP16

JMP9

JMP10

DAC Out

VSS

V H

REF

TP4

TP3

VCC

GND

VSS

GND

VDD

+5VA

+3.3VA

DIN

LDAC

SCLK

SYNC

JMP5

JMP6

JMP4

JMP3

JMP8

V H

REF

TP2

VSS

VCC

V L

REF

Output

Buffer

Module

Overview

The DAC8554EVM is designed to provide a demonstration platform for testing certain operationalcharacteristics of the DAC8554 digital-to-analog converter. Functional evaluation of the DAC8554 can beaccomplished with the use of any microprocessor, TI DSP or some sort of waveform generator.

Headers J2A (top side) and J2B (bottom side) are pass-through connectors provided to interface a hostprocessor or waveform generator with the DAC8554EVM using a custom-built cable. These connectorsenable the control signals and data to pass between the host and the device.

A mating adapter interface card (5-6k adapter interface) is also available to fit with TI’s TMS320C5000 andTMS320C6000 DSP Starter Kits (DSKs). This card resolves most of the trouble involved with building acustom cable. Additionally, there is also an MSP430-based platform (HPA449) that uses the MSP430F449microprocessor, to which this EVM can connect and interface as well. For more details or informationregarding the 5-6k adapter interface card or the HPA449 platform, please contact your Texas Instrumentsrepresentative, visit the TI web site or email the Data Converter Applications Support Team at[email protected].

The DAC outputs can be monitored through the selected pins of the J4 header connector. All outputs canbe switched through their respective jumpers—JMP11, JMP12, JMP13 and JMP14—for the purpose ofstacking. Stacking allows a total of eight DAC channels to be used, provided the A0 and A1 addresssignals are unique for each EVM board stacked.

In addition, the option of selecting one DAC output that can be fed to the noninverting side of the outputop amp, U2, is also possible by using a jumper across the selected pins of J4. The output op amp (U2)must first be correctly configured for the desired waveform characteristic. For more information, refer toSection 3 of this user’s guide.

A block diagram of the EVM is shown in Figure 1 .

Figure 1. DAC8554EVM Functional Block Diagram

SBAU121 – January 2006 DAC8554EVM User's Guide 3

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2 PCB Design and Performance

2.1 PCB Layout

PCB Design and Performance

1.3.1 Related Documentation from Texas Instruments

The following documents provide information regarding Texas Instrument integrated circuits used in theassembly of the DAC8554EVM. The latest revisions of these documents are available from the TI web siteat http://www.ti.com.

Data Sheet Literature NumberDAC8854 Datasheet SLAS431REF02 Datasheet SBVS003OPA627 Datasheet SBOS165OPA2132 Datasheet SBOS054

This section discusses the layout design of the DAC8554EVM PCB, describing the physical andmechanical characteristics of the EVM as well as a brief description of the demonstration board testperformance procedures performed. The list of components used in this evaluation module is alsoincluded.

The DAC8554EVM is designed to preserve the performance quality of the DAC8554, the device undertest (DUT), as specified in the data sheet. In order to take full advantage of the EVM capabilities, use careduring the schematic design phase to properly select the right components and to build the circuitcorrectly. The circuit design should include adequate bypassing, identifying and managing the analog anddigital signals, and understanding the components' electrical and mechanical attributes.

The primary design concerns during the layout process are optimal component placement and propersignal routing. Place the bypass capacitors as close as possible to the device pins, and properly separatethe analog and digital signals from each other. In the layout process, carefully consider the placement ofthe power and ground planes. A solid plane is ideal, but because of its greater cost, a split plane cansometimes be used satisfactorily. When considering a split plane design, analyze the componentplacement and carefully split the board into its analog and digital sections starting from the DUT. Theground plane plays an important role in controlling the noise and other effects that otherwise contribute tothe error of the DAC output. To ensure that the return currents are handled properly, route the appropriatesignals only in their respective sections, meaning that the analog traces should only lay directly above orbelow the analog section and the digital traces in the digital section. Minimize trace length, but use thelargest possible trace width allowable within the design. These design practices are illustrated in Figure 2through Figure 8 .

The DAC8554EVM board is constructed on a four-layer PCB using a copper-clad FR-4 laminate material.The PCB has a dimension of 43,1800mm (1.7000in) by 82,5500mm (3.2500in), and the board thickness is1,5748mm (0.062in). Figure 3 through Figure 7 show the individual artwork layers.

Note: Board layouts are not to scale. These are intended to show how the board is laid out; theyare not intended to be used for manufacturing DAC8554EVM PCBs.

DAC8554EVM User's Guide4 SBAU121 – January 2006

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PCB Design and Performance

Figure 2. DAC8554EVM PCB—Top Silkscreen Image

Figure 3. DAC8554EVM PCB—Layer 1 (Top Signal Layer)

SBAU121 – January 2006 DAC8554EVM User's Guide 5

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PCB Design and Performance

Figure 4. DAC8554EVM PCB—Layer 2 (Ground Plane)

Figure 5. DAC8554EVM PCB—Layer 3 (Power Plane)

DAC8554EVM User's Guide6 SBAU121 – January 2006

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PCB Design and Performance

Figure 6. DAC8554EVM PCB—Layer 4 (Bottom Signal Layer)

Figure 7. DAC8554EVM PCB—Bottom Silkscreen Image

SBAU121 – January 2006 DAC8554EVM User's Guide 7

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400mil

47.5mil

2700mil

3250mil

1300mil

1700mil

1247.5mil 1247.5mil

Notes:

1. PWB to be fabricated to meet or exceed IPC-6012

Class 3 standards and workmanship shall conform

to IPC-A-600, Class 3 - current revisions.

2. Board material and construction to be UL-Approved

and marked on the finished board.

3. Laminate material: Copper-Clad FR-4.

4. Copper weight: 1 oz. finished, all layers.

5. Finished thickness: .062 ±.010.

6. Min plating thickness in through holes: .001in.

7. SMOBC / HASL.

8. LPI soldermask both sides using appropriate

layer artwork, color = green.

9. LPI silkscreen as required: color = white.

10. Vendor information to be incorporated on back side

whenever possible.

11. Minimum copper conductor width is: 7 mils.

Minimum conductor spacing is: 7 mils.

12. Number of finished layers: 4.

13. Board dimensions: 3.250 in x 1.7 in.

50 15mil 0.381 mm PTH

43 23.622mil 0.6mm PTH

42 39.37mil 1mm PTH

5 40mil 1.016mm PTH

6 47.244mil 1.2mm PTH

1 63mil 1.6002mm PTH

147 total

2.2 EVM Performance

PCB Design and Performance

Figure 8. DAC8554EVM—Drill Drawing

The EVM performance test is executed using a high-density DAC bench test board, an Agilent 3458Adigital multimeter and a PC running LabVIEW™ software. The EVM board is tested for linearity for allcodes between 485 and 64741. The DUT is then allowed to settle for 1ms before the meter is read. Thisprocess is repeated for all codes to generate the measurements for INL and DNL.

Results of the DAC8554EVM tests are shown in Figure 9 through Figure 12 .

DAC8554EVM User's Guide8 SBAU121 – January 2006

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PCB Design and Performance

Figure 9. INL and DNL Characterization Graph of DAC A

SBAU121 – January 2006 DAC8554EVM User's Guide 9

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PCB Design and Performance

Figure 10. INL and DNL Characterization Graph of DAC B

DAC8554EVM User's Guide10 SBAU121 – January 2006

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