Texas Instruments SN65DSI83 EVM Bedienungsanleitung

SLLU221–October 2016

SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and

Implementation Guide

User's Guide

SLLU221–October 2016

SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s

Manual and Implementation Guide

This document describes how to use and configure the SN65DSI83, SN65DSI84, or SN65DSI85 EVM.

Hereafter in this document, the SN65DSI83, SN65DSI84, and SN65DSI85 devices may be referred to as

SN65DSI8X.

Contents

1 Overview...................................................................................................................... 2

1.1 What are the SN65DSI83, SN65DSI84, and SN65DSI85? ................................................... 2

1.2 What is the SN65DSI8X EVM? ................................................................................... 2

1.3 What is Included in the SN65DSI8X EVM? ..................................................................... 3

1.4 What Does This EVM Look Like? ................................................................................ 3

2 Hardware Description ....................................................................................................... 4

2.1 Connectors for DSI8X Input Ports................................................................................ 4

2.2 Connectors for DSI85 Output Ports .............................................................................. 4

2.3 I2C.................................................................................................................... 5

2.4 Enable or Reset..................................................................................................... 5

2.5 Power................................................................................................................. 5

2.6 Backlight Driver ..................................................................................................... 5

2.7 Reference CLK Programmability ................................................................................. 6

2.8 DIP Switch Configuration .......................................................................................... 6

3 Quick Start Guide............................................................................................................ 6

4 References ................................................................................................................... 7

5 EVM Schematics............................................................................................................. 8

List of Figures

1 SN65DSI8XEVM............................................................................................................. 3

2 SN65DSI8X EVM Block Diagram.......................................................................................... 4

3 DSI EVM Example Setup................................................................................................... 7

4 SN65DSI8X Schematic 1................................................................................................... 8

5 SN65DSI8X Schematic 2................................................................................................... 9

6 SN65DSI8X Schematic 3 ................................................................................................. 10

7 SN65DSI8X Schematic 4.................................................................................................. 11

List of Tables

1 SN65DSI8X Features Summary........................................................................................... 2

2 DIP Switch Setting........................................................................................................... 6

Overview

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1 Overview

1.1 What are the SN65DSI83, SN65DSI84, and SN65DSI85?

The SN65DSI8X is a MIPI DSI-to-LVDS bridge device that supports video modes in the forward direction.

The SN65DSI8X is primarily targeted for portable applications such as tablets and smart phones that

utilize the MIPI DSI video format. Use the SN65DSI8X between a GPU with DSI output and a video panel

with LVDS inputs.

All three devices share the same pin out and package.

Table 1 is a summary of the feature sets on these devices:

Table 1. SN65DSI8X Features Summary

Part Name Description Max Resolution

SN65DSI83 Single-channel DSI to single-link LVDS Suitable 1366×768/1280×60 fps at 24 bpp/18 bpp

SN65DSI84 Single-channel DSI to two single-link LVDS 1920×1200 60 fps at 24 bpp/18 bpp

SN65DSI85 Dual-channel DSI to two single-link LVDS 2560×1600 60 fps, 1920×1080p 120 fps at 24 bpp /18 bpp

NOTE: Each DSI channel has 4 DSI data lanes + 1 CLK lane. Each LVDS link has 4 data lanes + 1

CLK lane.

1.2 What is the SN65DSI8X EVM?

The SN65DSI8X EVM is a PCB created to help customers implementing SN65DSI83, SN65DSI84, and

SN65DSI85 in system hardware. This EVM can be used as a hardware reference design for any

implementation using the SN65DSI8X. The SN65DSI8X EVM is designed for use across all three versions

of the DSI bridge devices - SN65DSI83, SN65DSI84, and SN65DSI85. PCB design and layout files are

provided upon request to aid PCB design with a SN65DSI8X component. The layout files are used as a

guideline to implement the SN65DSI8X with illustrations of the routing and placement rules. Please note

that the EVM design includes test components to evaluate the SN65DSI8X which may not applicable for

production.

This EVM includes on-board connectors for DSI input and LVDS output signals. These connectors

connect MIPI DPHY-compliant DSI source and LVDS panels to the EVM. Refer to Section 2.1 and

Section 2.2 for more information on the connectors.

CAUTION

A custom translator cable or card is required if this EVM is to be utilized for the

evaluation of an implementation from the customer. Any other method of

connecting to any DSI source or LVDS panel is not supported by this EVM. TI

is not responsible for any issues or problems that may occur as a result of

using connection methods other than what is recommended in this document.

NOTE: Some portions and components in the EVM or in this document may include the references

to SN65DSI85 instead of addressing all three part numbers. The SN65DSI85 is replaceable

with SN65DSI83 or SN65DSI84.

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Overview

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1.3 What is Included in the SN65DSI8X EVM?

The major components of the EVM follow:

• SN65DSI83, SN65DSI84, or SN65DSI85

• Backlight driver via J2 and J5

• Samtec QSH-type connectors on DSI and LVDS interfaces

• Hirose-type connector on DSI Ch A interface

• IPEX-type connectors on LVDS interfaces

• I2C programming interface for external I2C host connection

1.4 What Does This EVM Look Like?

Figure 1 illustrates the EVM.

Figure 1. SN65DSI8XEVM

3.3V

1.8V

DSI85

DSI85 Input LVDS Output

I2C Logic Reset Logic

Backlight Driver

CDC -

Optional RefCLK

generation

Hirose

FX Conn

SMA/

Samtec

DSI_CHA_CLK

DSI_CHB_CLK

DSI_CHA_DATAP/N[3:0]

DSI_CHB_DATAP/N[3:0]

LVDS_CHA_CLK

LVDS_CHB_CLK

LVDS_CHA_DATAP/N[3:0]

LVDS_CHB_DATAP/N[3:0]

I-PEX

20455

SMA/

Samtec

Ref_CLK IN

Page 2

Page 3 Page 3

Page 3,5

Page 5

Page 4 Page 4

Page 4

Hardware Description

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2 Hardware Description

Figure 2 shows the EVM block diagram.

Figure 2. SN65DSI8X EVM Block Diagram

2.1 Connectors for DSI8X Input Ports

The EVM has two input options for DSI video. If a custom breakout board is to be designed using these

options, a schematic and an allegro PCB symbol for either connector is provided by TI upon request.

(A) J4 - Samtec QSH-type connector (P/N QSH-020-01-H-D-DP-A)

J4 is a Samtec QSH-type connector that can be mated with a matching QTH-type connector on the

top. It provides DSI input connections to both DSI Ch A and Ch B signals. It also provides access to

I2C and other miscellaneous signals such as IRQ. XC connections are open vias just in case there is a

need for connection to other signals. The mating connector part number is QTH-020-01-H-D-DP-A. For

an SMA-type connection, use the Samtec HDR-128291-XX breakout board. The HDR-128291-XX is a

breakout board with a mating connector to J4 and standard SMA male connectors via cables. More

information on this breakout board is provided upon request.

(B) J1 – Hirose FX-type connector (P/N FX6A-40S-0.8SV2)

J1 is a Hirose FX-type connector that can be mated with a matching FX plug on the top. The part

number for the mating connector is FX6A-40P-0.8SV2. J1 provides DSI input connection only to the

DSI Ch A signals. It also provides access to I2C and other miscellaneous signals such as IRQ.

2.2 Connectors for DSI85 Output Ports

There are two output port options available on the EVM for the LVDS output signals. If a custom breakout

board is to be designed using these options, a schematic and an allegro PCB symbol for either connector

can be provided by TI.

(A) J6 - Samtec QSH-type connector (P/N QSH-020-01-H-D-DP-A)

J6 is a Samtec QSH-type connector that can be mated with a matching QTH-type connector on the

top. It provides DSI input connections to both LVDS Ch A and Ch B signals. It also provides access to

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Hardware Description

SLLU221–October 2016

SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and

Implementation Guide

the backlight power and its related signals. XC connections are open vias, in case there is a need to

connect to other signals. The mating connector part number is QTH-020-01-H-D-DP-A. For an SMA-

type connection, use the Samtec HDR-128291-XX breakout board. The HDR-128291-XX is a breakout

board with a mating connector to J6 and standard SMA male connectors via cables. More information

on this breakout board is provided upon request.

(B) J2 and J5 – I-PEX-type connectors (P/N 20455-040E-12)

J2 and J5 are I-PEX connectors widely used in LCD video panels with LVDS receivers. Connect J2

and J5 via an SGC-type cable with one-to-one pin mapping to a panel using the I-PEX20455-040E-12

connectors. J2 connects to the LVDS Ch A signals while J5 connects to the LVDS CHB signals.

2.3 I2C

Access to I2C signals are provided via DSI input connectors J1 and J4 (as mentioned in Section 2.1) or

J10. Note that I2C signal levels should be at 1.8 V when the I2C interface is accessed through connectors

J1 or J4. A 3.3-V to 1.8-V voltage translation is provided when an I2C host is connected through J10.

A stand-alone external I2C host can be connected via J10 to debug.

2.4 Enable or Reset

There are three device enable or reset options to use with the EVM:

(A) Supervisor circuitry option

This is a default configuration. The enable (EN) signal is held low until the power good (PG) from the

1.8-V voltage regulator reaches a stable high voltage level, then it is released high.

(B) RC timing option

The C10 external capacitor and internal resistor are used to control the EN ramp time after the device

is powered on. C10 is a DNI (Do Not Install option), by default. C10 needs to be installed and R52

needs to be uninstalled to enable this option.

A push button (SW1) or a DIP switch (SW2.3) is available for the manual control of the EN signal.

Install R64 to enable the DIP switch option.

2.5 Power

A 5- to 6-V power supply will operate the SN65DSI8X EVM. A plug to accept a 5- to 6-V wall power

adapter is provided on the EVM (J13). The jumper on position 1-2 of J15 should be placed while J14 is

left open. This should be the default configuration when the board is shipped.

The EVM is designed to accommodate up to maximum of 1.5 A current. The current consumption of

the board without backlight driver enabled is about 70 mA + SN65DSI85 device power. The

SN65DSI85 consumes about 50 mA at power on, approximately 80 mA to approximately 200 mA,

depending on the system configuration. The total power consumption of the board could vary

depending on LCD panels when the on-board backlight driver is used. When an LCD panel consumes

more current than 1.5 A minus 70 mA + SN65DSI85 device power, an external backlight source should

be used.

NOTE: Do not plug in any power source higher than the configured voltage (5 V or 6 V).

2.6 Backlight Driver

The SN65DSI8X EVM incorporates the LED backlight driver circuitry using the TI backlight driver device

TPS61181A enabling use of the on-board backlight driver source. The default configuration of the EVM

enables the on-board backlight driver.

If the external backlight driver is used, a connection is available via J3. Uninstall FB6 if external backlight

driver is used.

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2.7 Reference CLK Programmability

The SN65DSI8X EVM incorporates a programmable CLK circuitry using a TI-programmable device,

CDCEL913. The output of the CDCEL913 is connected to the reference CLK of the SN65DSI8X. The

default frequency of the reference CLK is 27 MHz. The CLK can be programmed via I2C signals brought

out to on-board connectors J9, J12, or J10. When J10 is used, place jumpers on J9 and J12. The

reference CLK can be pre-programmed to a desired value, if requested prior to shipping.

2.8 DIP Switch Configuration

A DIP switch is provided to operate the device or EVM in different configurations. When the switch is in an

open position, the corresponding signal is tied high. When the switch is in the ON (closed) position, the

corresponding signal is tied to GND.

The signals in the greyed out region are not enabled unless a corresponding resistor is installed.

Table 2. DIP Switch Setting

DIP SW No Signal Name Description Default Configuration

Open(Off)

HIGH Closed(On)

LOW

SW2-1 DIP1 – Dimming CTRL or

LED_BKLT_EN

Controls LED backlight driver enable in default

configuration.

Installing R100 and uninstalling R63 enables

control on dimming control of the backlight

driver.

Always switch back to closed (ON) position

prior to unplug or plug operation of the panel.

SW2-2 I2C_3V3EN Enables 3.3-V voltage translator for the I2C

signals x

SW2-3 BRD_RSTN Controls the EN/RESET signal of the

SN65DSI8X high or low x

SW2-4 RSVD1 Reserved x

SW2-5 RSVD2 Reserved x

SW2-6 ADDR Controls the ADDR signal of the SN65DSI8X

high or low x

SW2-7 PWMIN Controls the PWMIN of J6 high or low x

SW2-8 LED_EN

Controls the LED_EN of J2 or J5 high or low

This switch should be toggled high to enable

the LED of the connected panel.

Always switch back to closed (ON) position

prior to unplug or plug operation of the panel.

3 Quick Start Guide

Quick-start instructions are provided in the following list:

1. Plug in a DSI source to J4

2. Plug in a LVDS video sink device on J2, J5 or J6

3. Plug in an I2C host on J10 if an external I2C host is used.

4. Make sure the DIP switch setting is in a correct configuration.

5. Apply power to the EVM. The following LEDs should light up: D3, D6, and D7. D1 may light up

depending on the configuration.

6. Start video streaming on the DSI input

7. Configure the device for the desired mode of operation via I2C. Video output should be observed after

configuration is complete.

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References

SLLU221–October 2016

SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and

Implementation Guide

Figure 3 depicts the setup using an external I2C host, Samtec-to-SMA breakout board (HDR-128291-XX)

for DSI ChA input and a 1024×600 video panel over an I-PEX connector.

Figure 3. DSI EVM Example Setup

4 References

1. SN65DSI8X Datasheets (SN65DSI83 SLLSEC1), (SN65DSI84 SLLSEC2), (SN65DSI85 SLLSEB9)

LEAVE

UNCONNECTED

FOR NORMAL

OPERATI ON

ADDR = 1, Slave Addr = 0x2D

ADDR = 0, Slave Addr = 0x2C

Reset(EN) can be implemented with passive

components as shown or active circuitry. In

case of using passive components, the

values of the RC circuitry need to be

adjusted to make sure the low to high

transition occurs after the Vcc supply has

reached the minimum recommended

operating voltage. For this reason, it is

recommended to USE ACTIVE CIRCUITRY for

better control of the RESET/EN timing.

DSI INPUT LVDS OUTPUT

Optional ref CLK

for LVDS Pixel

CLK

25MHz-154MHz

1uF is min value.

The number of capacitors and their values may vary depending on the system implementation

R5: Terminate to GND

with a pull-down

resistor if unused

0.2uF

SN65DSI85

Reset Implementation

Note: Bypass caps and FB

should be placed near U1

SN65DSI85.

*IMPORTANT*

If REFCLK is to be

used, the CLK trace

length between the

REFCLK terminal and

the source of the REF

CLK(OSC or Xtal)

should be kept as short

as possble.

IRQ

SilkScreen:

SilkScreen: IRQ

SilkScreen: REF_CLK

DSI_A0P

DSI_A0N

DSI_A1N

DSI_A2P

DSI_A2N

DSI_A3P

DSI_A3N

DSI_ACLKP

DSI_ACLKN

DSI_A1P

FlatChA_Y0N

FlatChA_Y0P

FlatChA_Y1P

FlatChA_Y2N

FlatChA_Y2P

FlatChA_Y3N

FlatChA_Y3P

FlatChA_YCLKN

FlatChA_YCLKP

FlatChA_Y1N

ADDR

Test1

Test2

BOARD_RESETN

IRQ

DSI_B0P

DSI_B0N

DSI_B1N

DSI_B2P

DSI_B2N

DSI_B3P

DSI_B3N

DSI_BCLKP

DSI_BCLKN

DSI_B1P

FlatChB_Y0P

FlatChB_Y0N

FlatChB_Y1P

FlatChB_Y2N

FlatChB_Y2P

FlatChB_Y3N

FlatChB_Y3P

FlatChB_YCLKN

FlatChB_YCLKP

FlatChB_Y1N

I2C_SCL

I2C_SDA

BOARD_RESETN

Vcore_1P1_Out

IRQ_LED

IRQ IRQ_OUT

REFCLK

EXT_REFCLK

Vcc_1P8V

BOARD_1P8V

BOARD_1P8V BOARD_1P8V

Vcc_1P8V

BOARD_1P8V BOARD_3P3V

DSI_A0Ppg3

DSI_A0Npg3

DSI_A1Ppg3

DSI_A1Npg3

DSI_A2Ppg3

DSI_A2Npg3

DSI_A3Ppg3

DSI_A3Npg3

DSI_ACLKPpg3

DSI_ACLKNpg3

DSI_B0Ppg3

DSI_B0Npg3

DSI_B1Ppg3

DSI_B1Npg3

DSI_B2Ppg3

DSI_B2Npg3

DSI_B3Ppg3

DSI_B3Npg3

DSI_BCLKPpg3

DSI_BCLKNpg3

I2C_SCL pg3,4

I2C_SDA pg3,4

LVDS_RefCLK pg4

FlatChA_Y0N pg3

FlatChA_Y0P pg3

FlatChA_Y1N pg3

FlatChA_Y1P pg3

FlatChA_Y2N pg3

FlatChA_Y2P pg3

FlatChA_Y3N pg3

FlatChA_Y3P pg3

FlatChA_CLKN pg3

FlatChA_CLKP pg3

FlatChB_Y0N pg3

FlatChB_Y0P pg3

FlatChB_Y1N pg3

FlatChB_Y1P pg3

FlatChB_Y2N pg3

FlatChB_Y2P pg3

FlatChB_Y3N pg3

FlatChB_Y3P pg3

FlatChB_CLKN pg3

FlatChB_CLKP pg3

BOARD_RESETNpg2,3,4

ADDRpg4

IRQ pg3

Test1pg4

Test2pg4

4.7K

R32

DNI

J17

HDR2X1 M .1

C11

1uF

10uF

10000pF

TP1

T POINT S

1.0uF

10K

10000pF

LED Orange 0805

10000pF

SN65DSI85

DA0P

DA1P

DA2P

DA3P

DACP

DB0P

DB1P

DB2P

DB3P

DBCP

DA0N

DA1N

DA2N

DA3N

DACN

DB0N

DB1N

DB2N

DB3N

DBCN

A_Y0N C9

A_Y1N D9

A_Y2N E9

A_Y3N G9

A_CLKN F9

A_Y0P C8

A_Y1P D8

A_Y2P E8

A_Y3P G8

A_CLKP F8

B_Y0N A3

B_Y0P B3

B_Y1N A4

B_Y1P B4

B_Y2N A5

B_Y2P B5

B_Y3N A7

B_Y3P B7

B_CLKN A6

B_CLKP B6

ADDR

SDA J1

SCL H1

TEST2

B2 TEST1

REFCLK H2

IRQ J9

Vcc A9

Vcc B8

Vcc D6

Vcc E6

Vcc F6

Vcc J2

Vcc E5

GND

Vcore J8

0.1uF

348

LP3

LP2LP1

FB1

220 @ 100MHZ C4

0.1uF

R33 0

4.7K

C10

DNI

SN74LVC1G07DCK

EVM Schematics

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5 EVM Schematics

Figure 4 through Figure 7 illustrate the EVM schematics.

Figure 4. SN65DSI8X Schematic 1

NOTE:

This connector is to interface DSIA Ch

using FX64-40P-0.8SV Type plug.

DSI ChA Display

Expansion Connector

BOTTOM VIEW

NOTE:

- Remove R6-R15 for DSI source connected to J4

- Populate R6-R15 when a source connected through J1

**R6 - R15 to be placed as near as J4 to avoid stub when J1 is not in use**

WARNING

20455-040E-12 has no

pin1 datum mark.

20455-040E-0X series

is same connector

with pin1 datum mark,

however the datum

mark is on the

opposite end of where

pin 1 is.

Note: This header is for supplying backlight

power

to flat panels with LED backlight. The pinout

mathces the connector definition of the back

light driver TPS61181 EVM.

Samtec to SMA Connector for DSIA and DSIB

NOTE:

This connector is to interface DSI interface

with any source with SMA connectors via

Samtec to SMA cable

Samtec to SMA Connector for Flatlink

NOTE:

This connector is to interface

Flatlink LVDS interfaceto LCD

Panels via breakout boards with

Flatlink LCD panel connector

Note: Bypass

caps.

Note: Bypass

caps.

Note: Bypass

caps

Note: Bypass

caps.

I-PEX 20455 Flatpanel Connectors

Flat ChA

SilkScreen:

Flat ChB

SilkScreen:

Timer_PWM

GPIO

PWM1

FX_CLKP

FX_CLKN

FX_P0

FX_N0

FX_P1

FX_N1

FX_P2

FX_N2

FX_P3

FX_N3

BL_PWR

IFB1

IFB2

IFB3

S_PWMIN

FlatA_20455_YP1

FlatA_20455_YN1

FlatA_20455_YP2

FlatA_20455_YN2

FlatA_20455_CLKP

FlatA_20455_CLKN

FlatA_20455_YN3

FlatA_20455_YP3

FlatA_20455_YP0

FlatA_20455_YN0FlatChA_Y0N

FlatChA_Y0P

FlatChA_Y1N

FlatChA_Y1P

FlatChA_Y2N

FlatChA_Y2P

FlatChA_CLKN

FlatChA_CLKP

FlatChA_Y3N

FlatChA_Y3P

IFB6

IFB4

IFB2

BL_PWR

IFB5

IFB3

IFB1

BL_PWR BL_PWR

LED_EN

BL_PWR

IFB4

IFB5

IFB6

S_PWMIN

FlatB_20455_YP1

FlatB_20455_YN1

FlatB_20455_YN2

FlatB_20455_CLKP

FlatB_20455_CLKN

FlatB_20455_YP3

FlatB_20455_YP0

FlatB_20455_YN0FlatChB_Y0N

FlatChB_Y0P

FlatChB_Y1N

FlatChB_Y1P

FlatChB_Y2N

FlatChB_Y2P

FlatChB_CLKN

FlatChB_CLKP

FlatChB_Y3N

FlatChB_Y3P

FlatB_20455_YN3

FlatB_20455_YP2

S_PWMIN

IFB6

IFB5

IFB4

IFB3

IFB2

IFB1

BL_PWR

LED_EN

S_PWMIN

J6_3P3V

J6_26

BOARD_3P3V

Panel_3P3V

BOARD_3P3V

Panel_3P3V

I2C_SCL pg2,3,4

I2C_SDA pg2,3,4

IRQ pg2,3

LED_ENpg3,4

IFB1 pg5

IFB3 pg5

IFB5 pg5

BL_PWRpg5

IFB2pg5

IFB4pg5

IFB6pg5

S_PWMINpg4

LED_ENpg3,4

DSI_ACLKPpg2,3

DSI_ACLKNpg2,3

DSI_A0Ppg2,3

DSI_A0Npg2,3

DSI_A1Ppg2,3

DSI_A1Npg2,3

DSI_A2Ppg2,3

DSI_A2Npg2,3

DSI_A3Ppg2,3

DSI_A3Npg2,3

FlatChA_Y1N pg2

FlatChA_Y1P pg2

FlatChA_Y2N pg2

FlatChA_Y2P pg2

FlatChA_CLKN pg2

FlatChA_CLKP pg2

FlatChA_Y3N pg2

FlatChA_Y3P pg2

FlatChA_Y0N pg2

FlatChA_Y0P pg2

FlatChB_Y0Npg2

FlatChB_Y0Ppg2

FlatChB_Y1Npg2

FlatChB_Y1Ppg2

FlatChB_Y2Npg2

FlatChB_Y2Ppg2

FlatChB_CLKNpg2

FlatChB_CLKPpg2

FlatChB_Y3Npg2

FlatChB_Y3Ppg2

IRQpg2,3

I2C_SCLpg2,3,4

DSI_B0Ppg2

DSI_B0Npg2

DSI_B1Ppg2

DSI_B1Npg2

DSI_BCLKPpg2

DSI_BCLKNpg2

DSI_B2Ppg2

DSI_B2Npg2

DSI_B3Ppg2

DSI_B3Npg2

DSI_A3P pg2,3

DSI_A3N pg2,3

DSI_A2P pg2,3

DSI_A2N pg2,3

DSI_ACLKP pg2,3

DSI_ACLKN pg2,3

DSI_A1P pg2,3

DSI_A1N pg2,3

DSI_A0P pg2,3

DSI_A0N pg2,3

I2C_SDA pg2,3,4

BOARD_RESETN pg2,4

XC7

C12

100uF

R43 0

TOP

J6 QSH-020-01

R70 0

R17 0

R25 0

R28 0

R30 DNI

R18 0

C13

1.0uF

R42 0

R12

XC11

C14

0.1uF

XC1

R45 0

FB2

220 @ 100MHZ

C21

DNI

R19 0

R14

R27 DNI

R31

FX6A-40S-0.8SV2(71)

I-PEX 20455-040E-12

GND1

GND3

GND2

GND4

R39 0

XC6

XC9

R20 0

R46 0

XC12

C20

DNI

R50 0

HEADER 7X2 100mil Thru-hole

R21 0

R13

C18

1.0uF

R40 0

R47 0

R15

C19

0.1uF

R49 DNI

R11

TOP

J4 QSH-020-01

C17

100uF

R22 0

C16

DNI

XC4

R41 0

R48 0

R23 0

FB3

220 @ 100MHZ

R16

DNI

R29 0

XC2

C15

DNI

R44 0

R24 0

XC3

XC5

R10

XC8

I-PEX 20455-040E-12

GND1

GND3

GND2

GND4

R26 0

www.ti.com

EVM Schematics

SLLU221–October 2016

SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and

Implementation Guide

Figure 5. SN65DSI8X Schematic 2

RESET

ADDR

PWMIN

LED_EN

BRD_RSTN

DIP1

I2C_3V3EN

CDC

I2C

DIPSW

SilkScreen:

CDC_S0

CDC_S1

CDC_S2

SilkScreen:

SilkScreen: I2C

CDC_SDA_ON

CDC_SCL_ON

NOTE:

SHUNT on CDC_SDA and CDC_SCL pin1 and 2 if external I2C host

via J10 for I2C programming of CDC device

SilkScreen:

TEST1

TEST2

ADDR

PWMIN

LED_EN

BRD_RSTN

SilkScreen:

DIP1

LED_BKLT_EN

Dim_CTRL

GND

SilkScreen: GND

GNDSilkScreen:

CDC_VDD

CDC_Y3

CDC_S0

CDC_XIN

CDC_Y1

CDC_S1_SDA

CDC_XOUT

CDC_S2_SCL

CDC_Y2

RESET#

BRD_RST_DIP

TEST1_DIP

A1_SDA

I2C_3V3EN

GND

I2C_SCL_3P3V

I2C_SDA_3P3V

BOARD_RESETN

ADDR_DIP

TEST2_DIP

I2C_3V3EN

I2C_SDA

I2C_SCL

GP_DIP

BOARD_RESETN

A1_SCL

LED_EN

LED_BKLT_EN

DimmingCTRL

GP_DIP

BOARD_RESETN

ADDR

S_PWMIN

CDC_CLKY2

CDC_CLKY3

BOARD_1P8V

BOARD_1P8VBOARD_1P8V

BOARD_1P8V BOARD_3P3V

BOARD_3P3V

BOARD_1P8V

BOARD_3P3V

BOARD_1P8V

LVDS_RefCLK pg2

PGpg5

BOARD_RESETNpg2,3

LED_ENpg3

I2C_SDA pg2,3

I2C_SCL pg2,3

ADDRpg2

S_PWMINpg3

TEST2pg2

TEST1pg2

DimmingCTRLpg5

LED_BKLT_ENpg5

N.O.

SW1

PB_SWITCH

R54

4.7K

R57

4.7K

J16

HEADER 1x10

R65 DNI

J12

HDR3X1 M .1

R77

4.7K

R74

10K

R63 0

txs0102dcut

OE 6

GND

A2 4

A1 5

VCCB

7VCCA 3

1B1

R71 0

XC10

J10

Header 5x2 0.1" thru-hole

HDR3X1 M .1

HDR2X1 M .1

1 2

CDCEL913PW

XIN_CLK

VDD 3

VCTR

GND

VDDOUT 6

VDDOUT 7

Y3 8

Y2 9

GND

Y1 11

S2_SCL

12 S1_SDA

XOUT

C27

22uF

R37 DNI

C24

18pF

R72

10K

R59

4.7K

J11

HDR2X1 M .1

1 2

R52

C55

DNI

C30

0.1uF

R73

10K

C32

0.1uF

R64 DNI

XC13

R78

4.7K

R76 0

C33

0.1uF

C31

0.1uF

R61

4.7K

FB4

220 @ 100MHZ

R66

DNI

R62 DNI

R75 0

C26

DNI

R51

DNI

HDR2X1 M .1

1 2

C25

DNI

R67 18

R60

4.7K

C29

0.1uF

R53

R58

4.7K

V c c

SN74LVC1G08DCK

TPS3808

TPS3808g18DBVT

RESET#

GND

MR#

3CT 4

SENSE 5

VDD 6

R68 18

27MHZ _crystal

R56

4.7K

C22

220pF

R55

4.7K

C23

0.1uF

SW2

8-POS 50-MIL SMT

TDA08H0SK1R

C&K (ITT-CANNON)

R69 18 C28

1.0uF

EVM Schematics

www.ti.com

10 SLLU221–October 2016

Submit Documentation Feedback

SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and

Implementation Guide

Figure 6. SN65DSI8X Schematic 3

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