Xilinx I2S Bedienungsanleitung
I2S Transmier and I2S
Receiver v1.0
LogiCORE IP Product Guide
Vivado Design Suite
PG308 (v1.0) April 4, 2018
Table of Contents
Chapter 1: IP Facts......................................................................................................... 4
Features........................................................................................................................................4
IP Facts..........................................................................................................................................4
Chapter 2: Overview......................................................................................................6
Applications..................................................................................................................................6
Unsupported Features................................................................................................................6
Licensing and Ordering.............................................................................................................. 6
Chapter 3: Product Specification........................................................................... 8
Performance................................................................................................................................ 9
Resource Use............................................................................................................................... 9
Port Descriptions.......................................................................................................................10
I2S Transmitter Register Space............................................................................................... 11
I2S Receiver Register Space..................................................................................................... 16
Chapter 4: Designing with the Core................................................................... 22
General Design Guidelines.......................................................................................................23
Clocking...................................................................................................................................... 24
Resets..........................................................................................................................................24
Programmimg Sequence......................................................................................................... 24
Interrupts................................................................................................................................... 25
Audio AXIS Interface................................................................................................................. 25
Chapter 5: Design Flow Steps.................................................................................27
Customizing and Generating the Core...................................................................................27
Constraining the Core...............................................................................................................30
Simulation.................................................................................................................................. 31
Synthesis and Implementation................................................................................................31
Chapter 6: Example Design..................................................................................... 32
Implementing the Example Design........................................................................................ 33
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Simulating the Example Design.............................................................................................. 33
Test Bench for Example Design...............................................................................................34
Appendix A: Debugging............................................................................................ 35
Finding Help on Xilinx.com...................................................................................................... 35
Hardware Debug.......................................................................................................................37
Appendix B: Additional Resources and Legal Notices............................. 38
Xilinx Resources.........................................................................................................................38
Documentation Navigator and Design Hubs.........................................................................38
References..................................................................................................................................39
Training Resources....................................................................................................................39
Revision History.........................................................................................................................39
Please Read: Important Legal Notices................................................................................... 40
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Chapter 1
IP Facts
The Xilinx® LogiCORE™ IP I2S Transmier and LogiCORE™ Receiver cores are so Xilinx IP cores
for use with the Xilinx Vivado® Design Suite, which makes it easy to implement inter-IC-sound
(I2S) interface used to connect audio devices for transming and receiving PCM audio.
Features
• AXI4-Stream compliant
• Supports up to four I2S channels (upto eight Audio channels)
• 16/24 bit data
• Supports Master I2S mode
•Congurable FIFO depth
• Supports the AES channel status extracon/inseron
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported Device Family1UltraScale+™, UltraScale™, Zynq®-7000 SoC, 7 series, Zynq®
UltraScale+™ MPSoC.
Supported User Interfaces AXI4-Lite, AXI4-Stream, AXI4
Resources Performance and Resource Use web page for transmitter
and Performance and Resource Use web page for receiver.
Provided with Core
Design Files System Verilog
Example Design System Verilog
Test Bench System Verilog
Constraints File Delivered at the time of IP generation
Simulation Model Source HDL
Supported S/W Driver2Standalone
Chapter 1: IP Facts
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LogiCORE IP Facts Table
Tested Design Flows 3
Design Entry Vivado® Design Suite Vivado IP Integrator
Simulation For supported simulators, see the Xilinx Design Tools:
Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx® at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP catalog.
2. Standalone driver details can be found in the software development kit (SDK) directory (<install_directory>/SDK/
<release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from the
Xilinx Wiki page.
3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
Chapter 1: IP Facts
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Chapter 2
Overview
The I2S Tramsmier and I2S Receiver cores provide an easy way to interface the I2S based audio
DAC/ADC. These IPs require minimal register programming and also support any audio sampling
rates. These IPs can be used along side HDMI, DisplayPort, and SDI for complete audio video
soluon.
Applications
Typical applicaons for I2S interfaces could be audio and video conferencing equipment,
consumer mul-media devices, professional audio sources, and sinks. The I2S Tramsmier and
I2S Receiver IPs can be used to develop audio soluon using I2S ADC/DACs. These IPs are
typically used with video connecvity IPs such as HDMI and Display Port to play or insert the
audio.
Unsupported Features
The following features of the standard are not supported in the core:
•Le and right jused I2S
• Data width of 20
• Slave mode
• Decode/encode user informaon bits
Licensing and Ordering
This Xilinx® LogiCORE™ IP module is provided at no addional cost with the Xilinx® Vivado®
under the terms of the Xilinx End User License.
Chapter 2: Overview
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Note: To verify that you need a license, check the License column of the IP Catalog. Included means that a
license is included with the Vivado® Design Suite; Purchase means that you have to purchase a license to
use the core.
For more informaon about this core, visit the I2S Tramsmier and I2S Receiver product web
page
Informaon about other Xilinx® LogiCORE™ IP modules is available at the Xilinx Intellectual
Property page. For informaon about pricing and availability of other Xilinx LogiCORE IP modules
and tools, contact your local Xilinx sales representave.
License Checkers
If the IP requires a license key, the key must be veried. The Vivado® design tools have several
license checkpoints for gang licensed IP through the ow. If the license check succeeds, the IP
can connue generaon. Otherwise, generaon halts with error. License checkpoints are
enforced by the following tools:
• Vivado Synthesis
• Vivado Implementaon
• write_bitstream (Tcl command)
Note: IP license level is ignored at checkpoints. The test conrms a valid license exists. It does not check IP
license level.
Chapter 2: Overview
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Chapter 3
Product Specification
The I2S Tramsmier and I2S Receiver IPs can be used to develop audio soluon using I2S ADC/
DACs. These IPs support any sampling rate and are very easy to congure with minimal register
programming.
Figure 1: TX Audio Sampling
AES3 Audio
Decoder FIFO
Register
Interface
I2S TX
I2S Timing
Gen
Sdata[3:0]
SCK
LRCLK
AXIS Audio (AES3)
s_axis_aud_aclk
aud_mclk
AXI4Lite
s_axi_ctrl_aclk
X20717-042318
Chapter 3: Product Specification
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Figure 2: RX Audio Sampling
AES3 Audio
Encoder FIFO
Register
Interface
I2S RX
I2S Timing
Gen
SData[3:0]
SCK
LRCLK
AXIS Audio (AES3)
m_axis_aud_aclk
AXI4Lite
s_axi_ctrl_aclk
aud_mclk
X20720-042318
Performance
For full details about performance and resource use, visit the Performance and Resource Use web
page for transmier and Performance and Resource Use web page for receiver.
Resource Use
For full details about performance and resource use, visit the Performance and Resource Use web
page for transmier and Performance and Resource Use web page for receiver.
Chapter 3: Product Specification
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Port Descriptions
Port Names
Table 1: Port Names
Port Name I/O Clock Description
Transmitter Ports
s_axi_ctrl_aclk I Clock Input clock for AXI4-Lite Interface
s_axi_ctrl_aresetn I Reset Active-Low reset for AXI4-Lite Interface
s_axi_ctrl_* s_axi_ctrl AXI4-Lite Interface
aud_mclk I Clock Input audio clock. Typically a multiple of Fs
aud_mrst I Reset Active-High reset for audio interface
s_axis_aud_aclk I Clock AXIS Audio streaming clock
s_axis_aud_resetn I Reset Active-Low AXIS audio reset
s_axis_aud_* Audio AXIS
Interface
AXIS Audio Interface
Irq O Interrupt Active-High interrupt
lrclk_out O LRClk Output LR Clock. Available when core is configured
as Master
sclk_out O SCLK Output SCK Clock. Available when core is
configured as Master
lrclk_in I LRClk Input LR Clock. Available when core is configured
as Slave
Sclk_in I SCLK Input SCK Clock. Available when core is configured
as Slave
sdata_0_out O SDATA0 I2S Serial Data out
sdata_1_out O SDATA1 I2S Serial Data out. Available when number of
audio channels is > 2
sdata_2_out O SDATA2 I2S Serial Data out. Available when number of
audio channels is > 4
sdata_3_out O SDATA3 I2S Serial Data out. Available when number of
audio channels is > 6
Receiver Ports
s_axi_ctrl_aclk I Clock Input clock for AXI4-Lite Interface
s_axi_ctrl_aresetn I Reset Active-Low reset for AXI4Lite Interface
s_axi_ctrl_* s_axi_ctrl AXI4Lite Interface
aud_mclk I Clock Input audio clock. Typically a multiple of Fs
aud_mrst I Reset Active-High reset for audio interface
m_axis_aud_aclk I Clock AXIS Audio streaming clock
m_axis_aud_resetn I Reset Active-Low AXIS audio reset
m_axis_aud_* Audio AXIS
Interface
AXIS Audio Interface
Chapter 3: Product Specification
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