Atmel AT91 Series Bedienungsanleitung

Features

•Incorporates the ARM7TDMI™ARM®Thumb®Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE (In-Circuit Emulation)

•On-chip SRAM and/or ROM

–32-bitDataBus

– Single-clock Cycle Access

•Fully Programmable External Bus Interface (EBI)

– Maximum External Address Space of 64M Bytes

– Upto8ChipSelects

– Software Programmable 8/16-bit External Databus

•8-level Priority, Individually Maskable, Vectored Interrupt Controller

– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request

•32 Programmable I/O Lines

•3-channel 16-bit Timer/Counter

– 3 External Clock Inputs

– 2 Multi-purpose I/O Pins per Channel

•2USARTs

– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART

•Programmable Watchdog Timer

•Advanced Power-saving Features

– CPU and Peripheral Can be Deactivated Individually

•Available in a 100-lead TQFP Package

Description

The AT91X40 Series is a subset of the Atmel AT91 16/32-bit microcontroller family,

which is based on the ARM7TDMI processor core. This processor has a high-perfor-

mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low

power consumption. In addition, a large number of internally banked registers result in

very fast exception handling, making the device ideal for real-time control applications.

The AT91X40 Series features a direct connection to off-chip memory, including Flash,

through the fully programmable External Bus Interface (EBI). An eight-level priority

vectored interrupt controller, in conjunction with the Peripheral Data Controller signifi-

cantly improve the real-time performance of the device.

The devices are manufactured using Atmel’s high-density CMOS technology. By com-

bining the ARM7TDMI processor core with on-chip high-speed memory and a wide

range of peripheral functions on a monolithic chip, the Atmel AT91X40 Series is a fam-

ily of powerful microcontrollers that offer a flexible, cost-effective solution to many

compute-intensive embedded control applications.

Microcontroller Primary SRAM Bank Secondary SRAM Bank ROM

AT91M40800 8K Bytes – –

AT91R40807 8K Bytes 128K Bytes –

AT91M40807 8K Bytes – 128K Bytes

AT91R40008 256K Bytes – –

AT91

ARM®Thumb®

Microcontrollers

AT91M40800

AT91R40807

AT91M40807

AT91R40008

Rev. 1354D–ATARM–05/02

2AT91X40 Series

1354D–ATARM–05/02

Pin Configuration

Figure 1. AT91X40 Series Pinout (Top View)

P21/TXD1/NTRI

P20/SCK1

P19

P18

P17

P16

P15/RXD0

P14/TXD0

P13/SCK0

P12/FIQ

GND

P11/IRQ2

P10/IRQ1

VDDIO

VDDCORE

P9/IRQ0

P8/TIOB2

P7/TIOA2

P6/TCLK2

P5/TIOB1

P4/TIOA1

P3/TCLK1

GND

P2/TIOB0

P1/TIOA0

P0/TCLK0

D15

D14

D13

D12

VDDIO

D11

D10

GND

P31/A23/CS4

P30/A22/CS5

VDDIO

VDDCORE

P29/A21/CS6

P22/RXD1

NWR1/NUB

GND

NRST

NWDOVF

VDDIO

MCKI

P23

P24/BMS

P25/MCKO

GND

TMS

TDO

TCK

NRD/NOE

NWR0/NWE

VDDCORE

VDDIO

NWAIT

NCS0

NCS1

P26/NCS2

P27/NCS3

A0/NLB

A2A2

VDDIO

A10

A11

A12

A13

A14

GND

A15

A16

A17

A18

A19

P28/A20/CS7

GND

100-lead TQFP

116

100

TDI

AT91X40 Series

1354D–ATARM–05/02

Table 1. AT91X40 Series Pin Description

Module Name Function Type

Active

Level Comments

EBI A0 - A23 Address Bus Output –All valid after reset

D0 - D15 Data Bus I/O –

NCS0 - NCS3 Chip Select Output Low

CS4 - CS7 Chip Select Output High A23 - A20 after reset

NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option

NWR1 Upper Byte 1 Write Signal Output Low Used in Byte Write option

NRD Read Signal Output Low Used in Byte Write option

NWE Write Enable Output Low Used in Byte Select option

NOE Output Enable Output Low Used in Byte Select option

NUB Upper Byte Select Output Low Used in Byte Select option

NLB Lower Byte Select Output Low Used in Byte Select option

NWAIT Wait Input Input Low

BMS Boot Mode Select Input –Sampled during reset

AIC FIQ Fast Interrupt Request Input –PIO-controlled after reset

IRQ0 - IRQ2 External Interrupt Request Input –PIO-controlled after reset

TC TCLK0 - TCLK2 Timer External Clock Input –PIO-controlled after reset

TIOA0 - TIOA2 Multipurpose Timer I/O Pin A I/O –PIO-controlled after reset

TIOB0 - TIOB2 Multipurpose Timer I/O Pin B I/O –PIO-controlled after reset

USART SCK0 - SCK1 External Serial Clock I/O –PIO-controlled after reset

TXD0 - TXD1 Transmit Data Output Output –PIO-controlled after reset

RXD0 - RXD1 Receive Data Input Input –PIO-controlled after reset

PIO P0 - P31 Parallel IO Line I/O –

WD NWDOVF Watchdog Overflow Output Low Open-drain

Clock MCKI Master Clock Input Input –Schmidt trigger

MCKO Master Clock Output Output –

Reset NRST Hardware Reset Input Input Low Schmidt trigger

NTRI Tri-state Mode Select Input Low Sampled during reset

ICE TMS Test Mode Select Input –Schmidt trigger, internal pull-up

TDI Test Data Input Input –Schmidt trigger, internal pull-up

TDO Test Data Output Output –

TCK Test Clock Input –Schmidt trigger, internal pull-up

Power VDDIO I/O Power Power –

VDDCORE Core Power Power –

GND Ground Ground –

4AT91X40 Series

1354D–ATARM–05/02

Block Diagram Figure 2. AT91X40 Series

ARM7TDMI Core

Embedded

ICE

Reset

EBI: External Bus Interface

ASB

Controller

Clock

AIC: Advanced

Interrupt Controller

AMBA Bridge

EBI User

Interface

TC: Timer

Counter

TC0

TC1

TC2

USART0

USART1

2 PDC

Channels

2 PDC

Channels

PIO: Parallel I/O Controller

PS: Power Saving

Chip ID

WD: Watchdog

Timer

APB

ASB

NRST

D0-D15

A1-A19

A0/NLB

NRD/NOE

NWR0/NWE

NWR1/NUB

NWAIT

NCS0

NCS1

P26/NCS2

P27/NCS3

P28/A20/CS7

P29/A21/CS6

P30/A22/CS5

P31/A23/CS4

P0/TCLK0

P3/TCLK1

P6/TCLK2

P1/TIOA0

P2/TIOB0

P4/TIOA1

P5/TIOB1

P7/TIOA2

P8/TIOB2

NWDOVF

TMS

TDO

TDI

TCK

MCKI

P25/MCKO

P12/FIQ

P9/IRQ0

P10/IRQ1

P11/IRQ2

P13/SCK0

P14/TXD0

P15/RXD0

P20/SCK1

P21/TXD1/NTRI

P22/RXD1

P16

P17

P18

P19

P23

P24/BMS

RAM

ROM

Extended SRAM

AT91X40 Series

1354D–ATARM–05/02

Architectural

Overview

The AT91X40 Series Microcontrollers integrate an ARM7TDMI with its embedded ICE

interface, memories and peripherals. The series’architecture consists of two main

buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB).

Designed for maximum performance and controlled by the memory controller, the ASB

interfaces the ARM7TDMI processor with the on-chip 32-bit memories, the External Bus

Interface (EBI) and the AMBA™Bridge. The AMBA Bridge drives the APB, which is

designed for accesses to on-chip peripherals and optimized for low-power consumption.

The AT91X40 Series Microcontrollers implement the ICE port of the ARM7TDMI proces-

sor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for

target debugging.

Memories The AT91X40 Series Microcontrollers embed up to 256K bytes of internal SRAM, and

up to 128K bytes of ROM. The internal memories are directly connected to the 32-bit

data bus and are single-cycle accessible. This provides maximum performance of 0.9

MIPS/MHz by using the ARM instruction set of the processor, minimizing system power

consumption and improving the performance of separate memory solutions.

The AT91X40 Series Microcontrollers feature an External Bus Interface (EBI), which

enables connection of external memories and application-specific peripherals. The EBI

supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit

device. The EBI implements the early read protocol, enabling faster memory accesses

than standard memory interfaces.

Peripherals The AT91X40 Series Microcontrollers integrate several peripherals, which are classified

as system or user peripherals. All on-chip peripherals are 32-bit accessible by the

AMBA Bridge, and can be programmed with a minimum number of instructions. The

peripheral register set is composed of control, mode, data, status and enable/dis-

able/status registers.

An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip

USARTs and on- and off-chip memories address space without processor intervention.

Most importantly, the PDC removes the processor interrupt handling overhead, making

it possible to transfer up to 64K continuous bytes without reprogramming the start

address, thus increasing the performance of the microcontroller, and reducing the power

consumption.

System Peripherals The External Bus Interface (EBI) controls the external memory or devices via an 8-bit or

16-bit data bus, and is programmed through the Advanced Peripheral Bus (APB). Each

chip select line has its own programming register.

The Power Saving (PS) module implements the Idle Mode (ARM7TDMI core clock

stopped until the next interrupt) and enables the user to adapt the power consumption of

the microcontroller to application requirements (independent peripheral clock control).

The Advanced Interrupt Controller (AIC) controls the internal sources from the internal

peripherals and the four external interrupt lines (including the FIQ) to provide an inter-

rupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority

controller, and, using the Auto-vectoring feature, reduces the interrupt latency time.

The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user

to select specific pins for on-chip peripheral input/output functions, and general-purpose

input/output signal pins. The PIO controller can be programmed to detect an interrupt on

a signal change from each line.

6AT91X40 Series

1354D–ATARM–05/02

The Watchdog (WD) can be used to prevent system lock-up if the software becomes

trapped in a deadlock.

The Special Function (SF) module integrates the Chip ID, the Reset Status and the Pro-

tect registers.

User Peripherals Two USARTs, independently configurable, enable communication at a high baud rate in

Synchronous or Asynchronous Mode. The format includes start, stop and parity bits and

up to 8 data bits. Each USART also features a Timeout and a Time Guard register, facil-

itating the use of the two dedicated Peripheral Data Controller (PDC) channels.

The 3-channel, 16-bit Timer Counter (TC) is highly-programmable and supports Capture

or Waveform Modes. Each TC channel can be programmed to measure or generate dif-

ferent kinds of waves, and can detect and control two input/output signals. The TC also

has 3 external clock signals.

AT91X40 Series

1354D–ATARM–05/02

Associated

Documentation

Table 2. Associated Documentation

Product Information Document Title

AT91M40800

Internal architecture of processor

ARM/Thumb instruction sets

Embedded in-circuit-emulator

ARM7TDMI (Thumb) Datasheet

Pinout

Mechanical characteristics

Ordering information

AT91M40800 Summary Datasheet

Timings

DC characteristics

AT91M40800 Electrical Characteristics

AT91R40807

Internal architecture of processor

ARM/Thumb instruction sets

Embedded in-circuit-emulator

ARM7TDMI (Thumb) Datasheet

Pinout

Mechanical characteristics

Ordering information

AT91R40807 Summary Datasheet

Timings

DC characteristics

AT91R40807 Electrical Characteristics

AT91M40807

Internal architecture of processor

ARM/Thumb instruction sets

Embedded in-circuit-emulator

ARM7TDMI (Thumb) Datasheet

Pinout

Mechanical characteristics

Ordering information

AT91M40807 Summary Datasheet

Timings

DC characteristics

AT91M40807 Electrical Characteristics

AT91R40008

Internal architecture of processor

ARM/Thumb instruction sets

Embedded in-circuit-emulator

ARM7TDMI (Thumb) Datasheet

Pinout

Mechanical characteristics

Ordering information

AT91R40008 Summary Datasheet

Timings

DC characteristics

AT91R40008 Electrical Characteristics

8AT91X40 Series

1354D–ATARM–05/02

Product Overview

Power Supply The AT91x40 Series Microcontrollers have two types of power supply pins - VDDIO and

VDDCORE. However, the AT91M40800, the AT91M40807 and the AT91R40807 have

single-supply VDD, VDDIO and VDDCORE pins that have to be tied to the same volt-

age. For further details on power supplies and acceptable voltage range on VDD,

VDDIO and VDDCORE, refer to the product Summary Datasheet or the product Electri-

cal Characteristics datasheet.

Input/Output

Considerations

The AT91M40807, the AT91R40807 and the AT91R40008 accept voltage levels up to

their power supply limit on the pads.

The AT91M40800 Microcontroller I/O pads are 5V-tolerant, enabling it to interface with

external 5V devices without any additional components. 5V-tolerant means that the

AT91M40800 accepts 5V (3V) on the inputs even if it is powered at 3V (2V). Refer to the

AT91M40800 Electrical Characteristics datasheet for further details.

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maxi-

mum flexibility. It is recommended that in any application phase, the inputs to the

AT91X40 Series Microcontroller be held at valid logic levels to minimize the power

consumption.

Master Clock The AT91X40 Series Microcontrollers have a fully static design and work on the Master

Clock (MCK), provided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is

multiplexed with a general-purpose I/O line. While NRST is active, the MCKO stays low.

After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO

Controller must be programmed to use this pin as standard I/O line.

Reset Reset restores the default states of the user interface registers (defined in the user inter-

face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch

from address zero. Except for the program counter the ARM7TDMI registers do not

have defined reset states.

NRST Pin NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-

chronized internally to the MCK. The signal presented on MCK must be active within the

specification for a minimum of 10 clock cycles up to the rising edge of NRST, to ensure

correct operation. The first processor fetch occurs 80 clock cycles after the rising edge

of NRST.

Watchdog Reset The watchdog can be programmed to generate an internal reset. In this case, the reset

has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not

sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted

and the watchdog triggers the internal reset, the NRST pin has priority.

Emulation Function

Tri-state Mode The AT91X40 Series provides a tri-state mode, which is used for debug purposes. This

enables the connection of an emulator probe to an application board without having to

desolder the device from the target board. In tri-state mode, all the output pin drivers of

the AT91X40 Series Microcontroller are disabled.

AT91X40 Series

1354D–ATARM–05/02

To enter tri-state mode, the pin NTRI must be held low during the last 10 clock cycles

before the rising edge of NRST. For normal operation, the pin NTRI must be held high

during reset, by a resistor of up to 400K Ohm.

NTRI is multiplexed with I/O line P21 and USART 1 serial data transmit line TXD1.

Standard RS-232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1

is connected to a device not including this pull-up, the user must make sure that a high

level is tied on NTRI while NRST is asserted.

JTAG/ICE Debug ARM standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The

pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-

nected to a host computer via the external ICE interface.

In ICE Debug Mode, the ARM7TDMI core responds with a non-JTAG chip ID that identi-

fies the microcontroller. This is not fully IEEE1149.1 compliant.

Memory Controller The ARM7TDMI processor address space is 4G bytes. The memory controller decodes

the internal 32-bit address bus and defines three address spaces:

•Internal Memories in the four lowest megabytes

•Middle Space reserved for the external devices (memory or peripherals) controlled

by the EBI

•Internal Peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian Mode only.

Internal Memories The AT91X40 Series Microcontrollers integrate one or two banks of internal static

SRAM and/or one bank of ROM. All internal memories are 32 bits wide and single-clock

cycle accessible. Byte (8-bit), halfword (16-bit) or word (32-bit) accesses are supported

and are executed within one cycle. Fetching Thumb or ARM instructions is supported

and internal memory can store twice as many Thumb instructions as ARM ones.

All the AT91X40 Series Microcontrollers integrate a primary 8-Kbyte or 256-Kbyte

SRAM bank, accessible at address 0x0 (after the remap).

The AT91R40807 integrates a secondary SRAM memory bank of 128K bytes at

address 0x10 0000. This secondary bank can be used to emulate the ROM of the

AT91M40807.

The AT91M40807 Microcontroller integrates 128K bytes of internal ROM at address

0x10 0000. It offers a reduced-cost option of the AT91R40807 for high-volume applica-

tions in which the software is stable.

Using Internal Memories The primary RAM bank is always mapped at address 0x30 0000 before remap and at

address 0x0 after the remap, allowing ARM7TDMI exception vectors to be modified by

the software. Making the RAM bank accessible before remap allows the user to copy

ARM exception vectors and boot code into the bank prior to remap.

The rest of the bank can be used for stack allocation to speed up context saving and

restoration, or as data and program storage for critical algorithms.

Placing the SRAM on-chip and using a 32-bit data bus bandwidth maximizes microcon-

troller performance while minimizing system power consumption. The 32-bit bus

optimizes use of the ARM instruction set and offers the ability to process data wider than

16 bits, thus making optimal use of the ARM7TDMI advanced performance.

The capability to update application software dynamically in an internal SRAM bank

adds an extra dimension to the AT91X40 Series Microcontrollers.

10 AT91X40 Series

1354D–ATARM–05/02

ROM Emulation The AT91R40807 provides an ideal means of emulating the ROM version

AT91M40807. The secondary SRAM bank of the AT91R40807 is mapped to the same

address as the ROM of the AT91M40807. It is write-protected after a reset; writing 0x1

in the Memory Mode Register of the Special Function Module can disable this

protection.

At system power-up, the code is downloaded from an external non-volatile memory or

through a debugger to the on-chip secondary SRAM bank of the AT91R40807. After the

secondary SRAM bank write-protection is enabled, the application is in the same envi-

ronment as though it were running on an AT91M40807.

Boot Mode Select The ARM reset vector is at address 0x0. After the NRST line is released, the

ARM7TDMI executes the instruction stored at this address. This means that this

address must be mapped in non-volatile memory after the reset.

The input level on the BMS pin during the last 10 clock cycles before the rising edge of

the NRST selects the type of boot memory. The Boot Mode depends on BMS and

whether or not the AT91X40 Series Microcontroller has on-chip ROM or extended

SRAM (see Table 3).

The AT91R40807 supports boot in on-chip extended SRAM, for the purpose of emulat-

ing ROM versions. In this case, the microcontroller must first boot from external non-

volatile memory, and ensure that a valid program is downloaded in the on-chip extended

SRAM. Then, the NRST must be reasserted by external circuitry after the level on the

pin BMS is changed.

The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like

any standard PIO line.

Remap Command The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,

Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to

allow these vectors to be redefined dynamically by the software, the AT91X40 Series

Microcontrollers use a remap command that enables switching between the boot mem-

ory and the internal primary SRAM bank addresses. The remap command is accessible

through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control

devices (connected to chip selects 1 to 7) is required. The remap operation can only be

changed back by an internal reset or an NRST assertion.

Abort Control The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI

is asserted in the following cases:

•When accessing an undefined address in the EBI address space

•When writing to a write-protected internal memory area on the AT91R40807

Table 3. Boot Mode Select

BMS Product Boot Memory

AT91M40800 External 8-bit memory on NCS0

AT91R40807 Internal 32-bit extended SRAM

AT91M40807 Internal 32-bit ROM

AT91R40008 External 8-bit memory on NCS0

0 All External 16-bit memory on NCS0

Andere Handbücher für AT91 Series

Dieses Handbuch passt für folgende Modelle

Inhaltsverzeichnis

Andere Atmel Mikrocontroller Handbücher

Atmel

Atmel AT89STK-09 Bedienungsanleitung

Atmel

Atmel AVR042 Montage- und Bedienungsanleitung

Atmel

Atmel AVR461 Bedienungsanleitung

Atmel

Atmel SMART ATSAMC21MOTOR Bedienungsanleitung

Atmel

Atmel SMARTCARD XPRO Bedienungsanleitung

Atmel

Atmel STK200 Bedienungsanleitung

Atmel

Atmel AT88CK109STK3 Installationshandbuch

Atmel

Atmel AT91SAM9 Montage- und Bedienungsanleitung

Atmel

Atmel AT90USB162 Bedienungsanleitung

Atmel

Atmel AVR XMEGA-A3BU Montage- und Bedienungsanleitung

Atmel

Atmel AVR2054 Bedienungsanleitung

Atmel

Atmel AVR ATtiny15L Bedienungsanleitung

Atmel

Atmel AVR128 Montage- und Bedienungsanleitung

Atmel

Atmel ATZB-EVB-24-SMA Bedienungsanleitung

Atmel

Atmel AVR1612 Montage- und Bedienungsanleitung

Atmel

Atmel ATBTLC1000 BluSDK Bedienungsanleitung

Atmel

Atmel AVR XMEGA D Series Bedienungsanleitung

Atmel

Atmel AVR042 Montage- und Bedienungsanleitung

Atmel

Atmel AT89C2051 Bedienungsanleitung

Atmel

Atmel MC320 Bedienungsanleitung

Atmel

Atmel STK512 Bedienungsanleitung

Atmel

Atmel AT89C52 Bedienungsanleitung

Atmel

Atmel AVR AT90S2323 Bedienungsanleitung

Atmel

Atmel AVR4901 Montage- und Bedienungsanleitung

Beliebte Mikrocontroller Handbücher anderer Marken

AMS

AMS AS7261 Demo Kit Bedienungsanleitung

Novatek

Novatek NT6861 Bedienungsanleitung

Espressif Systems

Espressif Systems ESP8266 SDK Einrichtungshandbuch

Nuvoton

Nuvoton ISD61S00 ChipCorder Leitfaden

STMicrolectronics

STMicrolectronics ST7 Assembler Linker Bedienungsanleitung

Texas Instruments

Texas Instruments Chipcon CC2420DK Bedienungsanleitung

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM Bedienungsanleitung

NEC

NEC 78GK0S/K 1+ Series Montage- und Bedienungsanleitung

Mikroe

Mikroe SEMITECH N-PLC Click Montage- und Bedienungsanleitung

Intel

Intel Agilex Bedienungsanleitung

Cypress

Cypress CY4607 HX2VL Bedienungsanleitung

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE Bedienungsanleitung

Texas Instruments

Texas Instruments TMS320F2837 D Series Bedienungsanleitung

CYPRES

CYPRES CY14NVSRAMKIT-001 Bedienungsanleitung

Texas Instruments

Texas Instruments INA-DUAL-2AMP-EVM Bedienungsanleitung

Espressif Systems

Espressif Systems ESP8266EX Betriebsanleitung

Abov

Abov AC33M8128L Bedienungsanleitung

Laird

Laird BL654PA Bedienungsanleitung