Cmsemicon BAT32A2 9 Series Bedienungsanleitung

BAT32A2x9 User Manual | Chapter 1 CPU

www.mcu.com.cn 1 / 1149 Rev.1.00

BAT32A2x9 User Manual

An ultra-low-power 32-bit microcontroller based on the ARM®Cortex®-M0+

Rev 1.00

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BAT32A2x9 User Manual | Chapter 1 CPU

www.mcu.com.cn 2 / 1149 Rev.1.00

Documentation Instructions

This manual is a technical reference manual for BAT32A239/BAT32A279 microcontroller products, and the

technical reference manual is an application note on how to use this series of products, including the structure,

functional description, and function description of each functional module. Details such as operating modes and

The Technical Reference Manual is a description of all functional modules in this series of products, please

refer to the data sheet for the description of the characteristics of the product (i.e. the function carrying situation).

The data sheet information is as follows:

BAT32A239xx: BAT32A239_datasheet_vx.xx. pdf

BAT32A279xx: BAT32A279_datasheet_vx.xx. pdf

Usually in the early stage of chip selection, the first thing to see is to look at the data sheet to evaluate whether

the product can meet the functional requirements of the design; After basically selecting the required product, it is

necessary to check the technical reference manual to determine whether the working mode of each functional

module meets the requirements; When determining that the selection enters the programming design phase, a

detailed technical reference manual is required to understand the specific implementation of each function and the

current, drive capability, and pin assignment.

For a detailed description of the Cortex-M0+ core, SysTick timer, and NVIC, please refer to the documentation

for the corresponding ARM.

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BAT32A2x9 User Manual Chapter List

BAT32A239xx

BAT32A279xx

Chapter 1: CPU

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Chapter 2: Pin Functions

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Chapter 3: System structure

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Chapter 4: Clock generation circuit

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Chapter 5: Hardware Divider

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Chapter 6: Universal timer unit Timer4/8

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Chapter 7: TimerA

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Chapter 8: TimerB

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Chapter 9: TimerC

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Chapter 10: TimerM

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Chapter 11: Real-Time Clock

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Chapter 12: 15-Bit Interval Timer

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Chapter 13: Clock output/buzzer output control circuitry

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Chapter 14: Watchdog Timer

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Chapter 15: A/D Converter

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Chapter 16: D/A Converters

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Chapter 17: Comparator

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Chapter 18: Programmable Gain Amplifier

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Chapter 19: Universal Serial Communication Unit

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Chapter 20: Serial Interface IICA

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Chapter 21: Serial Interface SPI

╳

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Chapter 22: CAN Control

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Chapter 23: LCD Bus Interface

╳

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Chapter 24: Enhanced DMA

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Chapter 25: Linkage Controller

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Chapter 26: Interrupt function

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Chapter 27: Key Interrupt Function

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Chapter 28: Standby Function

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Chapter 29: Reset Function

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Chapter 30: Power-on Reset Circuit

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Chapter 31: Voltage Detection Circuit

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Chapter 32: Safety Functions

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Chapter 33: Temperature sensor and internal reference voltage

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Chapter 34: Option Bytes

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Chapter 35: Flash Control

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Index 
Documentation Instructions...............................................................................................................................2 
Chapter 1CPU.................................................................................................................................................25 
1 overview.........................................................................................................................................25 
2 Cortex-M0+ core features..............................................................................................................25 
3 Debug features..............................................................................................................................25 
4 SWD interface pin..........................................................................................................................27 
5 ARM reference documentation......................................................................................................28 
Chapter 2Pin function .....................................................................................................................................29 
1 Port capabilities .............................................................................................................................29 
2 Port multiplexing function ..............................................................................................................29 
3 Registers that control port functionality.........................................................................................30 
3.1 Port Mode Register (PMxx)......................................................................................................33 
3.2 Port register (Pxx).....................................................................................................................34 
3.3 Port Set Control Register (PSETxx).........................................................................................35 
3.4 Port Clear Control Register (PCLRxx)......................................................................................36 
3.5 Pull-up resistor selection register (PUxx).................................................................................37 
3.6 Port input mode register (PIMxx)..............................................................................................38 
3.7 Port output mode register (POMxx)..........................................................................................39 
3.8 Port Mode Control Register (PMCxx).......................................................................................40 
3.9 Port read-back register (PREADxx). ........................................................................................41 
3.10 Peripheral I/O redirect register 0 (PIOR0)................................................................................42 
3.11 Peripheral I/O redirect register 1 (PIOR1)................................................................................43 
3.12 Peripheral I/O redirect register 2(PIOR2).................................................................................44 
3.13 Peripheral I/O redirect register 3(PIOR3).................................................................................45 
3.14 Peripheral I/O redirect register 4 (PIOR4)................................................................................46 
3.15 Global Digital Input Disable Register (GDIDIS)........................................................................47 
4 Unused pin handling......................................................................................................................48 
5 Register settings when using the multiplexing function ................................................................49 
5.1 Basic principle when using the multiplexing feature ................................................................49 
5.2 Examples of register settings using the port function and the multiplexing function...............50 
Chapter 3System structure.............................................................................................................................69 
1 overview.........................................................................................................................................69 
2 System address partition...............................................................................................................70 
3 Peripheral address assignment.....................................................................................................72 
Chapter 4Clock generation circuit...................................................................................................................73 
1 Function of the clock generation circuit.........................................................................................73 
2 Structure of the clock generation circuit........................................................................................75 

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3 Control Registers of the clock generation circuit...........................................................................78 
3.1 Clock operating mode control register (CMC)..........................................................................78 
3.2 System Clock Control Register (CKC). ....................................................................................80 
3.3 Clock Operating State Control Register (CSC)........................................................................81 
3.4 PLL Control Register (PLLCR) for System Clock.....................................................................82 
3.5 The state register (OSTC) of the oscillation settling time counter ...........................................83 
3.6 Oscillation settling time selection register (OSTS)...................................................................85 
3.7 Peripheral enable registers 0, 1, 2, 3 (PER0, PER1, PER2, P ER2 PER3)............................86 
3.8 Subsystem clock supply mode control register (OSMC)..........................................................92 
3.9 Frequency Selection Register (HOCODIV) for high-speed internal oscillators .......................93 
3.10 Trimming Register (HIOTRM) for high-speed internal oscillator..............................................94 
3.11 Subsystem Clock Select Register (SUBCKSEL) .....................................................................95 
3.12 Master System Clock Control Register (MCKC)......................................................................96 
4 System clock oscillation circuit......................................................................................................97 
4.1 X1 oscillation circuit..................................................................................................................97 
4.2 XT1 oscillation circuit................................................................................................................97 
4.3 High-speed internal oscillator.................................................................................................101 
4.4 Low-speed internal oscillator..................................................................................................101 
5 Clock generation circuit operation...............................................................................................102 
6 Clock control................................................................................................................................104 
6.1 Example of setting up a high-speed internal oscillator...........................................................104 
6.2 Example of setting up the X1 oscillation circuit......................................................................106 
6.3 Example of setting up the XT1 oscillation circuit....................................................................107 
6.4 State transition graph of the CPU clock .................................................................................108 
6.5 Conditions before CPU clock transfer and processing after transfer.....................................114 
6.6 Time required to switch between the CPU clock and the master system clock ....................116 
6.7 Conditions before clock oscillation stops................................................................................117 
7 High-speed internal vibration correction function........................................................................118 
7.1 High-speed internal vibration self-adjustment function..........................................................118 
7.2 Register description................................................................................................................119 
7.3 Description of the operation....................................................................................................120 
7.4 Precautions for use.................................................................................................................123 
8 Vibration stop detection circuit ....................................................................................................124 
8.1 Vibration stops the function of the detection circuit................................................................124 
8.2 Composition of the vibration-stop detection circuit.................................................................124 
8.3 The register used by the oscillator stops detection circuit .....................................................125 
8.4 The operation of the vibration stop detection circuit ..............................................................127 
8.5 Precautions for vibration stop detection function...................................................................128 
Chapter 5Hardware divider...........................................................................................................................129 

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1 Features.......................................................................................................................................129 
2 Feature description......................................................................................................................129 
3 Registers for the hardware divider ..............................................................................................129 
3.1 DIVIDEND...............................................................................................................................130 
3.2 Divider (DIVISAR)...................................................................................................................130 
3.3 Quotient ..................................................................................................................................130 
3.4 REMAINDER ..........................................................................................................................130 
3.5 Status register (STATUS).......................................................................................................131 
Chapter 6Universal timer unit Timer4/8........................................................................................................132 
1 Functions of the universal timer unit............................................................................................134 
1.1 Stand-alone channel operation function.................................................................................134 
1.2 Multi-channel linkage operation function................................................................................136 
1.3 8-bit timer operation function (channel 1 and channel 3 of unit 0 only).................................137 
1.4 LIN-bus support function (limited to channel 3 of unit 0)........................................................137 
2 Structure of a universal timer unit................................................................................................138 
2.1 List of general-purpose timer unit registers............................................................................141 
2.2 Timer count register mn (TCRmn)..........................................................................................144 
2.3 Timer data register mn (TDRmn)............................................................................................146 
3 Control registers of the universal timer unit.................................................................................147 
3.1 Peripheral enable register 0 (PER0). .....................................................................................148 
3.2 Timer clock selection register m (TPSm)...............................................................................149 
3.3 Timer mode register mn (TMRmn).........................................................................................152 
3.4 Timer status register mn (TSRmn).........................................................................................156 
3.5 Timer channel enable status register m (TEm)......................................................................157 
3.6 Timer channel start register m(TSm)......................................................................................158 
3.7 Timer channel stop register m(TTm)......................................................................................159 
3.8 Timer input and output selection register (TIOS0).................................................................160 
3.9 Timer output enable register m (TOEm).................................................................................161 
3.10 Timer output register m (TOm)...............................................................................................162 
3.11 Timer output level register m(TOLm). ....................................................................................163 
3.12 Timer output mode register m (TOMm)..................................................................................164 
3.13 Input Select Control Register (ISC)........................................................................................165 
3.14 Noise filter enable registers (NFEN1/NFEN2)........................................................................166 
3.15 Registers that control the function of the timer input/output pin ports....................................167 
4 The basic rules of the universal timer unit...................................................................................168 
4.1 The basic rules of the multi-channel linkage operation function............................................168 
4.2 Timer channel start register m(TSm)......................................................................................170 
4.3 The basic rules for the 8-bit timer to operate the function (limited to Channel 1 and Channel 3 
of Unit 0). 171 

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5 The operation of the counter.......................................................................................................172 
5.1 Count clock (fTCLK). ..............................................................................................................172 
5.2 The start timing of the counter................................................................................................174 
5.3 The operation of the counter ..................................................................................................175 
6 Control of the channel output (TOmn pin)...................................................................................180 
6.1 Structure of the TOmn pin output circuit.................................................................................180 
6.2 Output setting of the TOmn pin..............................................................................................181 
6.3 Considerations for channel output operation .........................................................................182 
6.4 one-time operation of the TOmn bit........................................................................................186 
6.5 About the timer interrupt and TOmn pin output when starting to count.................................187 
7 Control of the timer input (TImn)..................................................................................................188 
7.1 Structure of the TImn pin input circuit.....................................................................................188 
7.2 Noise filters.............................................................................................................................188 
7.3 Considerations when operating channel input.......................................................................189 
8 Stand-alone channel operation of the universal timer unit..........................................................190 
8.1 Operation as an interval timer/square wave output................................................................190 
8.2 Run as an external event counter ..........................................................................................194 
8.3 Operation as a divider.............................................................................................................197 
8.4 Operation as input pulse interval measurements...................................................................200 
8.5 Operation as input signal high and low level width measurements.......................................203 
8.6 Runs as a delay counter.........................................................................................................207 
9 Multi-channel linkage operation function of the universal timer unit...........................................210 
9.1 Operation as a single-trigger pulse output function................................................................210 
9.2 Operates as a PWM function..................................................................................................217 
9.3 Operation as a multi-PWM output function.............................................................................224 
10 Considerations when using a universal timer unit.......................................................................232 
10.1 Considerations when using timer outputs..............................................................................232 
Chapter 7Timer A..........................................................................................................................................233 
1 Function of timer A.......................................................................................................................233 
2 Structure of timer A......................................................................................................................234 
3 Controls the registers of timer A..................................................................................................235 
3.1 Peripheral enable register 1 (PER1). .....................................................................................236 
3.2 The subsystem clock provides a mode control register (OSMC)...........................................237 
3.3 Timer A counts register 0 (TA0).............................................................................................238 
3.4 Timer A controls register 0 (TACR0)......................................................................................239 
3.5 Timer AI/O control register 0 (TAIOC0)..................................................................................240 
3.6 Timer A controls register 0 (TAMR0)......................................................................................242 
3.7 Timer A event pin select register 0 (TAISR0).........................................................................243 
3.8 Port mode register x (PMx).....................................................................................................244 

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4 Operation of timer A ....................................................................................................................245 
4.1 Overrides to reload registers and counters............................................................................245 
4.2 Timer mode.............................................................................................................................246 
4.3 Pulse output mode..................................................................................................................247 
4.4 Event counter pattern.............................................................................................................248 
4.5 Pulse width measurement mode............................................................................................250 
4.6 Pulse period measurement mode ..........................................................................................251 
4.7 Collaboration with EVENTC ...................................................................................................252 
4.8 Output settings for each mode ...............................................................................................252 
5 Considerations when using Timer A............................................................................................253 
5.1 Start and stop control of counting...........................................................................................253 
5.2 Access to flags (TEDGF bits and TUNDF bits of the TACR0 register)..................................253 
5.3 Access to the Counting register..............................................................................................253 
5.4 Change in Operational mode..................................................................................................254 
5.5 Setup steps for TAO pins and TAIO pins...............................................................................255 
5.6 When timer A is not used .......................................................................................................255 
5.7 Timer A runs the stop of the clock..........................................................................................255 
5.8 Setup steps for deep sleep mode (event counter mode).......................................................256 
5.9 Functional limitations in deep sleep mode (event counter mode only)..................................256 
5.10 Forced count stop via the TSTOP bit.....................................................................................256 
5.11 Digital filters............................................................................................................................256 
5.12 The case where fIL is selected as the count source..............................................................256 
Chapter 8Timer B..........................................................................................................................................257 
1 Function of timer B.......................................................................................................................257 
2Structure of timer B......................................................................................................................258 
3 Control registers of timer B..........................................................................................................259 
3.1 Peripheral enables register 1 (PER1).....................................................................................260 
3.2 Timer B mode register (TBMR). .............................................................................................261 
3.3 Timer B counts the control register (TBCNTC)......................................................................262 
3.4 Timer B Control Register (TBCR)...........................................................................................263 
3.5 Timer B interrupt enable register (TBIER)..............................................................................264 
3.6 Timer B status register (TBSR)..............................................................................................265
3.7 Timer BI/O Control Register (TBIOR).....................................................................................268 
3.8 Timer B counter (TB)..............................................................................................................270 
3.9 Timer B universal registers A, B, C, D (TBGRA, TBGRB, TBGRC, TBGRD)........................271 
3.10 Port registers and port mode registers...................................................................................273 
4 Operation of timer B ....................................................................................................................274 
4.1 Common things about multiple patterns and features ...........................................................274 
4.2 Timer mode (input capture function) ......................................................................................279 

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4.3 Timer mode (output comparison function)..............................................................................282 
4.4 PWM mode.............................................................................................................................286 
4.5 Phase count mode..................................................................................................................290 
5 Timer B interrupt..........................................................................................................................293 
6 Considerations when using timer B.............................................................................................295 
6.1 Phase difference, overlap, and pulse width in phase count mode.........................................295 
6.2 Switching modes.....................................................................................................................295 
6.3 Count the switching of the source..........................................................................................295 
6.4 Setup steps for TBIO0 pins and TBIO1 pins..........................................................................296 
6.5 External clocks TBBCLK0 and TBBCLK1..............................................................................296 
6.6 Read and write access to SFR...............................................................................................296 
6.7 Stop counting when the input snap runs................................................................................297 
Chapter 9Timer C .........................................................................................................................................298 
1 Function of timer C ......................................................................................................................298 
2 Structure of timer C .....................................................................................................................299 
3 Control registers of timer C..........................................................................................................300 
3.1 Peripheral enable register 1 (PER1). .....................................................................................300 
3.2 Timer C count register (TC)....................................................................................................301 
3.3 Timer C count buffer register (TCBUF)..................................................................................301 
3.4 Timer C controls register 1 (TCCR1)......................................................................................302 
3.5 Timer C controls register 1 (TCCR2)......................................................................................303 
3.6 Timer C status register (TCSR)..............................................................................................304 
4 Operation of timer C....................................................................................................................305 
4.1 Count the sources...................................................................................................................305 
4.2 Timer C starts counting the actions........................................................................................305 
4.3 Timer C counts stopped actions.............................................................................................308 
4.4 Enter the capture motion........................................................................................................309 
4.5 Timer C counts the reset action..............................................................................................310 
4.6 Interrupt of timer C..................................................................................................................312 
5 Precautions when using Timer C ................................................................................................313 
5.1 Read and write registers.........................................................................................................313 
5.2 Overflow interruption...............................................................................................................313 
5.3 Input capture and timer C count reset action.........................................................................313 
5.4 Timer C and Timer M, comparator 1 are linked .....................................................................313 
Chapter 10 Timer M...........................................................................................................................314 
1 Function of timer M......................................................................................................................314 
2 Structure of timer M.....................................................................................................................315 
3 Control register of timer M...........................................................................................................316 
3.1 Peripheral enable register 1 (PER1). .....................................................................................317 

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3.2 Timer M EVENTC register (TMELC)......................................................................................318 
3.3 Timer M Start Register (TMSTR)............................................................................................319 
3.4 Timer M mode register (TMMR).............................................................................................320 
3.5 Timer M PWM function select register (TMPMR)...................................................................321 
3.6 Timer M function control register (TMFCR)............................................................................322 
3.7 Timer M output master enable register 1 (TMOER1).............................................................323 
3.8 Timer M output main enable register 2 (TMOER2)................................................................324 
3.9 Timer M output control register (TMOCR)..............................................................................325 
3.10 The timer M digital filter function selects register i (TMDFi) (i=0, 1)........................................328 
3.11 Timer M controls register i (TMCRi) (i=0, 1)............................................................................330 
3.12 Timer M I/O control register Ai (TMIORAi)(i =0, 1).................................................................335 
3.13 Timer M I/O control register Ci (TMIORCi)(i=0, 1)..................................................................337 
3.14 Timer M status register 0 (TMSR0)........................................................................................339 
3.15 Timer M status register 1 (TMSR1)........................................................................................345 
3.16 Timer M interrupt enable register i (TMIERi) (i=0, 1)..............................................................351 
3.17 The timer MPWM function outputs level control register i (TMPOCRi) (i=0, 1). .....................352 
3.18 Timer M counter i(TMi) (i=0, 1)...............................................................................................353 
3.19 Timer M General Purpose registers Ai, Bi, Ci, Di...................................................................355 
3.20 Port mode registers (PMxx, PMCxx)......................................................................................364 
4 Common things about multiple patterns......................................................................................365 
4.1 Counting sources....................................................................................................................365 
4.2 The buffer operation ...............................................................................................................366 
4.3 Synchronous Operation..........................................................................................................369 
4.4 Forced cutoff of the pulse output............................................................................................370 
4.5 Event inputs from the Event Linkage Controller (EVENTC)...................................................372 
4.6 Event output to the Event Linkage Controller (EVENTC)/Data Transfer Controller (DMA)...372 
5 Operation of timer M....................................................................................................................373 
5.1 Enter the capture function ......................................................................................................373 
5.2 Output comparison function....................................................................................................378 
5.3 PWM function..........................................................................................................................384 
5.4 Reset synchronous PWM mode.............................................................................................388 
5.5 Complementary PWM mode ..................................................................................................391 
5.6 PWM3 mode...........................................................................................................................395 
6 Timer M interrupt.........................................................................................................................398 
7 Considerations when using timer M............................................................................................401 
7.1 Read and write access to SFR...............................................................................................401 
7.2 Switching modes.....................................................................................................................401 
7.3 Counting sources....................................................................................................................402 
7.4 Enter the capture function ......................................................................................................402 