Cmsemicon BAT32G137 Bedienungsanleitung

BAT32G137 User's Guide |Documentation Usage Instructions

www.mcu.com.cn 1 / 1052 V2.1.1

BAT32G137 User Manual

Ultra-low power 32-bit microcontroller based on ARM® Cortex®-M0+

Rev.2.1.1

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BAT32G137 User's Guide |Documentation Usage Instructions

www.mcu.com.cn 2 / 1052 V2.1.1

Documentation Instructions

This manual is the technical reference manual for the BAT32G137 microcontroller product. The technical

reference manual is the application instruction material on how to use this series of products, including the

structure, function description, working mode and register configuration of each functional module.

The technical reference manual is a description of all functional modules of this series of products. If you want

to know the feature description of the product (that is, the functional configuration), you can refer to the respective

data sheet.

The data sheet information is as follows：

BAT32G137xx：BAT32G137_datasheet_vx.x.x. pdf

Usually in the early stage of chip selection, you shall first check the data sheet to evaluate whether the product

can meet the functional requirements of the design; after basically selecting the required product, you need to check

the technical reference manual to determine whether the working mode of each functional module does meet the

requirement；When determining the selection and entering the programming design stage, you need to read the

technical reference manual in detail to understand the specific implementation and register configuration of each

function. Refer to the data sheet for information on voltages, currents, drive capabilities, and pin assignments when

designing hardware。

For a detailed description of the Cortex-M0+ core, SysTick timer and NVIC, please refer to the respective ARM

documents.

BAT32G137 User's Guide |Documentation Usage Instructions 
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Index 
Documentation Instructions ................................................................................... 2
Chapter 1 CPU....................................................................................................................... 20 
1 verview................................................................................................................................................................... 20 
2 Cortex-M0+ core features...................................................................................................................................... 20 
3 Debug features...................................................................................................................................................... 20 
4 SWD interface pin.................................................................................................................................................. 22 
5 ARM reference document...................................................................................................................................... 23 
Chapter 2 Pin function.......................................................................................................... 24 
1 port function........................................................................................................................................................... 24 
2 port multiplex ......................................................................................................................................................... 24 
3 Register for controlling port function...................................................................................................................... 25 
3.1 Port Mode Register (PMxx) ................................................................................................................................. 27 
3.2 Port Register (Pxx).............................................................................................................................................. 28 
3.3 Pull-up resistance selection register (PUxx)........................................................................................................ 29 
3.4 Port input mode register (PIMxx)......................................................................................................................... 30 
3.5 Port output mode register (POMxx)..................................................................................................................... 31 
3.6 Port mode control register (PMCxx) .................................................................................................................... 32 
3.7 Peripheral I/O Redirection Register 0 (PIOR0).................................................................................................... 33 
3.8 Peripheral I/O Redirection Register 1 (PIOR1).................................................................................................... 35 
3.9 Peripheral I/O Redirection Register 2 (PIOR2).................................................................................................... 36 
3.10 Peripheral I/O Redirection Register 3 (PIOR3).................................................................................................... 37 
4 Handling of unused pins ........................................................................................................................................ 39 
5 Register Settings When Using Multiplexing........................................................................................................... 40 
5.1 The Basic principal of Using Multiplexing Function.............................................................................................. 40 
5.2 Examples of Register Settings for Port and Multiplexing Functions Used ........................................................... 41 
Chapter 3 system structure ................................................................................................. 51 
1 Overview................................................................................................................................................................ 51 
2 system address partitioning................................................................................................................................... 52 
Chapter 4 clock generator.................................................................................................... 54 
1 Function of clock generation circuit........................................................................................................................ 54 
2 Structure of clock generating circuit....................................................................................................................... 56 
3 Register for controlling clock generation circuit...................................................................................................... 58 
3.1 Clock Run Mode Control Register (CMC)............................................................................................................ 59 
3.2 System Clock Control Register (CKC)................................................................................................................. 60 
3.3 Clock Operational Status Control Register (CSC)............................................................................................... 61 
3.4 State register of the oscillation stabilization time counter (OSTC)....................................................................... 63 
3.5 Oscillating Stable Time Select Register (OSTS).................................................................................................. 65 
3.6 Peripheral Enable Registers 0, 1 (PER0, PER1)................................................................................................. 66 
3.7 Secondary system clock provides mode control register (OSMC)....................................................................... 71 
3.8 Frequency selection register (HOCODIV) for high speed internal oscillator........................................................ 72 

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3.9 High speed internal oscillator fine-tuned register (HIOTRM) ............................................................................... 73 
4 System clock oscillating circuit............................................................................................................................... 74 
4.1 X1 oscillating circuit............................................................................................................................................. 74 
4.2 XT1 oscillating circuit........................................................................................................................................... 74 
4.3 high speed internal oscillator............................................................................................................................... 78 
4.4 low-speed internal oscillator ................................................................................................................................ 78 
5 Operation of clock generation circuit...................................................................................................................... 79 
6 clock control........................................................................................................................................................... 81 
6.1 Example of high speed internal oscillator set-up ................................................................................................. 81 
6.2 An example of X1 oscillation circuit..................................................................................................................... 83 
6.3 Setting example of XT1 oscillation circuit............................................................................................................ 84 
6.4 CPU Clock State Transition Diagram .................................................................................................................. 85 
6.5 Conditions before CPU clock transfer and post-transfer processing ................................................................... 91 
6.6 Time required to switch CPU clock and main system clock................................................................................. 93 
6.7 Conditions before clock oscillation stops............................................................................................................. 94 
Chapter 5 hardware divider.................................................................................................. 95 
1 characteristics........................................................................................................................................................ 95 
2 Feature Description ............................................................................................................................................... 95 
3 Register for hardware divider................................................................................................................................. 95 
3.1 division register (DIVIDEND)............................................................................................................................... 96 
3.2 Divisor register (DIVISOR)................................................................................................................................... 96 
3.3 quotient register (QUOTIENT)............................................................................................................................. 96 
3.4 Remainder register (REMAINDER)..................................................................................................................... 96 
3.5 status register (STATUS) .................................................................................................................................... 97 
Chapter 6 Universal Timer Unit Timer4............................................................................... 98 
1 Function of universal timer unit............................................................................................................................ 100 
1.1 Stand-alone channel operation.......................................................................................................................... 100 
1.2 multi-channel coordinated operation function.................................................................................................... 102 
1.3 8-bit timer operation function (only for channel 1 and channel 3 of unit 0). ....................................................... 103 
1.4 LIN-bus support (Cell 0-only channel 3)............................................................................................................ 103 
2 Structure of universal timer unit........................................................................................................................... 104 
2.1 Universal timer unit register list.......................................................................................................................... 107 
2.2 Timer count register mn (TCRmn)..................................................................................................................... 108 
2.3 timer data register mn (TDRmn)........................................................................................................................ 110 
3 Register for controlling universal timer unit.......................................................................................................... 111 
3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 112 
3.2 Timer Clock Select Register m (TPSm)............................................................................................................. 113 
3.3 timer mode register mn (TMRmn)...................................................................................................................... 116 
3.4 timer status register mn (TSRmn)...................................................................................................................... 120 
3.5 Timer channel allows state register m (TEm) to be ........................................................................................... 121 
3.6 Timer channel start register m (TSm)................................................................................................................ 122 
3.7 Timer channel stop register m (TTm). ............................................................................................................... 123 
3.8 Timer Input-Output Selection Register (TIOS0, TIOS1) .................................................................................... 124 

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3.9 timer output allow register m (TOEm)................................................................................................................ 126 
3.10 Timer output register m (TOm).......................................................................................................................... 127 
3.11 Timer output level register m (TOLm)................................................................................................................ 128 
3.12 Timer output mode register m (TOMm) ............................................................................................................. 129 
3.13 Input switch control register (ISC)...................................................................................................................... 130 
3.14 Noise Filter Admission Register (NFEN1) ......................................................................................................... 131 
3.15 Register for controlling timer input/output pin port function................................................................................ 132 
4 Basic rules for universal timer units ..................................................................................................................... 133 
4.1 Basic Prinicpal of Multi-channel Coordinated Operation Function..................................................................... 133 
4.2 Basic Principal of the 8-bit timer operation function (only for channel 1 and channel 3).................................... 135 
5 Operation of counters .......................................................................................................................................... 136 
5.1 Count Clock (fTCLK) ......................................................................................................................................... 136 
5.2 Starting sequence of Counter............................................................................................................................ 138 
5.3 Operation of counters........................................................................................................................................ 139 
6 Control of channel output (TOmn pin).................................................................................................................. 144 
6.1 Structure of TOmn pin output circuit.................................................................................................................. 144 
6.2 Output settings for TOmn pins........................................................................................................................... 145 
6.3 Precaution for Channel Output Operation ......................................................................................................... 146 
6.4 One-time operation of TOmn bits ...................................................................................................................... 151 
6.5 About timer interrupts and TOmn pin output at start of counting ....................................................................... 152 
7 Control of timer input (TImn)................................................................................................................................ 153 
7.1 Structure of TImn pin input circuit...................................................................................................................... 153 
7.2 noise filter.......................................................................................................................................................... 153 
7.3 Precautions When Operating Channel Inputs ................................................................................................... 154 
8 Independent channel operation function of universal timer unit........................................................................... 155 
8.1 Operation as Interval Timer/Square wave Output.............................................................................................. 155 
8.2 Run as External Event Counter......................................................................................................................... 159 
8.3 Operation as a frequency divider (only for channel 0 of cell 0).......................................................................... 162 
8.4 Operation as an input pulse interval measurement ........................................................................................... 165 
8.5 Operation as voltage high and low level width measurement of input signal..................................................... 168 
8.6 Operation as delay counter ............................................................................................................................... 172 
9 Multi-channel coordinated operation function of universal timer unit ................................................................... 175 
9.1 Operation as single trigger pulse output function............................................................................................... 175 
9.2 Operation as PWM Function.............................................................................................................................. 182 
9.3 Operation as Multiple PWM Output Function..................................................................................................... 189 
10 Precautions when using a universal timer unit..................................................................................................... 197 
10.1 Precautions When Using Timer Output............................................................................................................. 197 
Chapter 7 Timer A............................................................................................................... 198 
1 Function of timer A............................................................................................................................................... 198 
2 Structure of timer A.............................................................................................................................................. 199 
3 Register for control timer A.................................................................................................................................. 200 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 200 
3.2 Secondary system clock provides mode control register (OSMC)..................................................................... 201 

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3.3 timer A count register 0 (TA0)............................................................................................................................ 202 
3.4 timer A control register 0 (TACR0). ................................................................................................................... 203 
3.5 Timer AI/O control register 0 (TAIOC0) ............................................................................................................. 204 
3.6 timer A control register 0 (TAMR0).................................................................................................................... 206 
3.7 Timer A Event Pin Selection Register 0 (TAISR0)............................................................................................. 207 
3.8 Port Mode Register x (PMx) .............................................................................................................................. 208 
4 Operation of timer A............................................................................................................................................. 209 
4.1 Reload register and counter override ................................................................................................................ 209 
4.2 timer mode......................................................................................................................................................... 210 
4.3 pulse output mode............................................................................................................................................. 211 
4.4 Event Counter Mode.......................................................................................................................................... 212 
4.5 pulse width measurement mode........................................................................................................................ 214 
4.6 pulse period measurement mode...................................................................................................................... 215 
4.7 Collaboration with EVENTC............................................................................................................................... 216 
4.8 Output settings for each mode........................................................................................................................... 216 
5 Precautions when using timer A .......................................................................................................................... 217 
5.1 Start and stop control of count........................................................................................................................... 217 
5.2 Access to flags (TEDGF and TUNDF bits of the TACR0 register)..................................................................... 217 
5.3 Access to a counter register.............................................................................................................................. 217 
5.4 Changes in Patterns.......................................................................................................................................... 218 
5.5 Set-up steps for TAO and TAIO pins................................................................................................................. 218 
5.6 When timer A not used...................................................................................................................................... 218 
5.7 Stopping execution clock of timer A................................................................................................................... 218 
5.8 Configuration steps for deep sleep mode (event counter mode)....................................................................... 219 
5.9 Functional limitations in deep sleep mode (event counter mode only) .............................................................. 219 
5.10 Forced count stop with TSTOP bit..................................................................................................................... 219 
5.11 digital filter ......................................................................................................................................................... 219 
5.12 The Case of Selecting fIL as Count Source....................................................................................................... 219 
Chapter 8 Timer B............................................................................................................... 220 
1 Function of timer B............................................................................................................................................... 220 
2 Structure of timer B.............................................................................................................................................. 221 
3 Register for control timer B.................................................................................................................................. 222 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 223 
3.2 timer B mode register (TBMR)........................................................................................................................... 224 
3.3 Timer B count control register (TBCNTC).......................................................................................................... 225 
3.4 Timer B Control Register (TBCR)...................................................................................................................... 226 
3.5 Timer B interrupt enable register (TBIER) ......................................................................................................... 227 
3.6 Timer B Status Register (TBSR)........................................................................................................................ 228 
3.7 Timer BI/O control register (TBIOR).................................................................................................................. 230 
3.8 Timer B Counter (TB) ........................................................................................................................................ 232 
3.9 timer b general register a, b, c, d....................................................................................................................... 233 
3.10 port register and port mode register .................................................................................................................. 235 
4 Operation of timer B............................................................................................................................................. 236 

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4.1 Common Issues Concerning Multiple Models and Functions............................................................................ 236 
4.2 timer mode (input capture function)................................................................................................................... 241 
4.3 timer mode (output comparison function).......................................................................................................... 244 
4.4 PWM mode........................................................................................................................................................ 248 
4.5 phase counting mode........................................................................................................................................ 252 
5 timer B interrupt................................................................................................................................................... 255 
6 Precautions when using timer B .......................................................................................................................... 257 
6.1 Phase difference, overlap and pulse width in phase counting mode................................................................. 257 
6.2 mode switching.................................................................................................................................................. 257 
6.3 Switch of count source ...................................................................................................................................... 257 
6.4 Set-up steps for TBIO0 and TBIO1 pins............................................................................................................ 258 
6.5 external clock TBCLK0 and TBCLK1................................................................................................................. 258 
6.6 Read and write access to SFR.......................................................................................................................... 258 
6.7 Input capture operation when stopping count.................................................................................................... 259 
Chapter 9 timer C................................................................................................................ 260 
1 Function of timer C .............................................................................................................................................. 260 
2 Structure of timer C.............................................................................................................................................. 261 
3 Register for controlling timer C ............................................................................................................................ 262 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 262 
3.2 timer C count register (TC)................................................................................................................................ 263 
3.3 timer C count buffer register (TCBUF)............................................................................................................... 263 
3.4 timer C control register 1 (TCCR1).................................................................................................................... 264 
3.5 timer C control register 1 (TCCR2).................................................................................................................... 265 
3.6 timer C status register (TCSR) .......................................................................................................................... 266 
4 Operation of timer C ............................................................................................................................................ 267 
4.1 count source...................................................................................................................................................... 267 
4.2 Timer C starts counting actions......................................................................................................................... 267 
4.2.1 Select the Timer M signal as the setting and action for the trigger.................................................................. 268 
4.2.2 Select the settings and actions when the software fires.................................................................................. 269 
4.3 Timer C counts stop actions.............................................................................................................................. 270 
4.3.1 Select Comparator 1 as Trigger Settings and Actions..................................................................................... 270 
4.3.2 Settings and actions when software is triggered ............................................................................................. 270 
4.4 Input capture action........................................................................................................................................... 271
4.5 timer C count reset action.................................................................................................................................. 272 
4.6 Interruption of timer C........................................................................................................................................ 274 
5 Precautions for Using Timer C............................................................................................................................. 275 
5.1 Read/write of register ........................................................................................................................................ 275 
5.2 overflow interrupt............................................................................................................................................... 275 
5.3 Input capture and timer C count reset actions................................................................................................... 275 
5.4 Steps when timer C and timer M and comparator 1 are linked.......................................................................... 275 
Chapter 10 Timer M.............................................................................................................. 276 
1 Function of timer M.............................................................................................................................................. 276 
2 Structure of timer M............................................................................................................................................. 277 

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3 Register for controlling timer M............................................................................................................................ 278 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 279 
3.2 timer M EVENTC register (TMELC)................................................................................................................... 280 
3.3 Timer M Start Register (TMSTR)....................................................................................................................... 281 
3.4 timer M mode register (TMMR).......................................................................................................................... 282 
3.5 Timer M PWM Function Selection Register (TMPMR) ...................................................................................... 283 
3.6 Timer M Functional Control Register (TMFCR)................................................................................................. 284 
3.7 Timer M outputs master permissive register 1 (TMOER1) ................................................................................ 285 
3.8 Timer M outputs Master Permissive Register 2 (TMOER2)............................................................................... 286 
3.9 Timer M Output Control Register (TMOCR) ...................................................................................................... 287 
3.10 timer m digital filter function selection register i (TMDFi) (i=0,1)........................................................................ 290 
3.11 Timer M control register i (TMCRi) (i=0,1)......................................................................................................... 292 
3.12 Timer MI/O control register Ai(TMIORAi) (i=0,1) ............................................................................................... 297 
3.13 Timer MI/O control register Ci(TMIORCi) (i=0,1)............................................................................................... 299 
3.14 Timer M Status Register 0 (TMSR0) ................................................................................................................. 301 
3.15 Timer M Status Register 1 (TMSR1) ................................................................................................................. 306 
3.16 timer m interrupt enable register i (TMIERi) (i=0,1) ........................................................................................... 312 
3.17 timer MPWM function output level control register i (TMPOCRi) (i=0,1)............................................................ 313 
3.18 timer M counter i (TMi) (i=0,1)........................................................................................................................... 314 
3.19 timer m general register ai, bi, ci, di................................................................................................................... 316 
3.20 Port Mode Register (PMxx, PMCxx).................................................................................................................. 325 
4 Common Issues on Multiple Models.................................................................................................................... 326 
4.1 count source...................................................................................................................................................... 326 
4.2 buffer operation ................................................................................................................................................. 327 
4.3 synchronous operation ...................................................................................................................................... 330 
4.4 Forced Cutoff of Pulse Output........................................................................................................................... 331 
4.5 Events entered from the Event Coordination Controller(EVENTC).................................................................... 333 
4.6 Events output to the event Coordination Controller(EVENTC)/data transfer controller (DMA) .......................... 334 
5 Operation of timer M............................................................................................................................................ 335 
5.1 Input capture function........................................................................................................................................ 335 
5.2 output comparison function ............................................................................................................................... 340 
5.3 PWM function.................................................................................................................................................... 345 
5.4 Reset synchronous PWM mode........................................................................................................................ 350 
5.5 complementary PWM mode .............................................................................................................................. 353 
5.6 PWM3 mode...................................................................................................................................................... 358 
6 Timer M interrupt ................................................................................................................................................. 360 
7 Precautions when using timer M.......................................................................................................................... 363 
7.1 Read and write access to SFR.......................................................................................................................... 363 
7.2 mode switching.................................................................................................................................................. 363 
7.3 count source...................................................................................................................................................... 364 
7.4 Input capture function........................................................................................................................................ 364 
7.5 Set-up steps for TMIOAi, TMIOBi, TMIOCi, TMIODi pins (i=0,1)....................................................................... 364 
7.6 external clock TMCLK ....................................................................................................................................... 365 
7.7 complementary PWM mode .............................................................................................................................. 365 

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8 PWMOP............................................................................................................................................................... 370 
8.1 Features of PWMOP ......................................................................................................................................... 371 
8.2 Register for PWMOP......................................................................................................................................... 371 
8.3 Running of PWMOP.......................................................................................................................................... 377 
8.3.1output forced cut-off ........................................................................................................................................ 377 
8.3.2Hardware Undoing (HS_SEL=0) ..................................................................................................................... 377 
8.3.3Software Undoing (HS_SEL=1)....................................................................................................................... 387 
8.3.4Hazard countermeasure.................................................................................................................................. 393 
8.3.5Output Force Cutoff of Source Checked Out and Unchecked Out.................................................................. 394 
8.3.6The time sequence diagram when the value of the counter of timer M reaches 0000 H................................. 394 
8.3.7Configuration Steps......................................................................................................................................... 396 
8.4 Precautions........................................................................................................................................................ 397 
Chapter 11 real-time clock .................................................................................................. 398 
1 The Function of Real-time Clock.......................................................................................................................... 398 
2 Structure of real-time clock.................................................................................................................................. 398 
3 Register for controlling real-time clock................................................................................................................. 400 
3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 401 
3.2 Real-time clock selection register (RTCCL)....................................................................................................... 402 
3.3 Real-time clock control register 0 (RTCC0)....................................................................................................... 403 
3.4 Real-time clock control register 1 (RTCC1)....................................................................................................... 404 
3.5 Clock error correction register (SUBCUD)......................................................................................................... 406 
3.6 Second Count Register (SEC)........................................................................................................................... 407 
3.7 Minute Count Register (MIN)............................................................................................................................. 407 
3.8 Hour count register (HOUR).............................................................................................................................. 408 
3.9 Day count register (DAY)................................................................................................................................... 410 
3.10 Week count register (WEEK)............................................................................................................................. 411 
3.11 Month count register (MONTH) ......................................................................................................................... 412 
3.12 Year count register (YEAR)............................................................................................................................... 412 
3.13 Alarm clock minute register (ALARMWM) ......................................................................................................... 413 
3.14 Alarm clock hour register (ALARMWH) ............................................................................................................. 413 
3.15 Alarm clock week register (ALARMWW)........................................................................................................... 413 
3.16 port mode register and port register .................................................................................................................. 414 
4 Operation of real-time clock................................................................................................................................. 415 
4.1 Real Time clock Operation start ........................................................................................................................ 415 
4.2 Transition to sleep mode after start of operation ............................................................................................... 416 
4.3 Real-time clock counter reading and writing...................................................................................................... 417 
4.4 Alarm setting for real-time clock ........................................................................................................................ 419 
4.5 1 Hz output of real-time clock............................................................................................................................ 420 
4.6 Example of clock deviation calibration for a real-time clock............................................................................... 421 
Chapter 12 15-bit interval timer .......................................................................................... 423 
1 The function of a 15-bit interval timer................................................................................................................... 423 
2 Structure of 15-bit interval timer........................................................................................................................... 423 
3 Register for controlling 15-bit interval timer.......................................................................................................... 424 

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3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 424 
3.2 Real-time clock selection register (RTCCL)....................................................................................................... 425 
3.3 Control register for 15-bit interval timer (ITMC) ................................................................................................. 426 
4 Operation of a 15-bit interval timer....................................................................................................................... 427 
4.1 Run-time sequence of 15-bit interval timer........................................................................................................ 427 
4.2 The operation of the counter is started after returning from the sleep mode and the transfer to the sleep mode is 
repeated............................................................................................................................................................ 428 
Chapter 13 Clock output/buzzer output control circuit .................................................... 429 
1 The Function of Clock Output/Buzzer Output Control Circuit............................................................................... 429 
2 Structure of clock output/buzzer output control circuit ......................................................................................... 430 
3 Register for control clock output/buzzer output control circuit.............................................................................. 430 
3.1 Clock output selection register n (CKSn)........................................................................................................... 430 
3.2 Register for controlling clock output/buzzer output pin port function.................................................................. 432 
4 Operation of clock output/buzzer output control circuit ........................................................................................ 433 
4.1 Operation of the Output Pin............................................................................................................................... 433 
5 Precautions for Clock Output/Buzzer Output Control Circuit................................................................................ 433 
Chapter 14 watchdog timer................................................................................................. 434 
1 Function of watchdog timer.................................................................................................................................. 434 
2 Structure of watchdog timer................................................................................................................................. 434 
3 Register for controlling watchdog timer................................................................................................................ 436 
3.1 Watchdog timer enable register (WDTE)........................................................................................................... 436 
3.2 WDTCFG configuration register (WDTCFG0/1/2/3) .......................................................................................... 437 
4 Operation of watchdog timer................................................................................................................................ 438 
4.1 Operation control of watchdog timer.................................................................................................................. 438 
4.2 Setting of overflow time of watchdog timer........................................................................................................ 439 
4.3 Watchdog timer window settings during opening............................................................................................... 440 
4.4 Setting of watchdog timer interval interrupt ....................................................................................................... 441 
4.5 Operation of watchdog timer when WDTCFG is not configured........................................................................ 441 
Chapter 15 A/D converter.................................................................................................... 442 
1 Functions of A/D Converter.................................................................................................................................. 442 
2 Register for controlling A/D converter.................................................................................................................. 444 
2.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 445 
2.2 Mode register 0 (ADM0) for A/D converter ........................................................................................................ 446 
2.3 Mode register 1 for A/D converter (ADM1) ........................................................................................................ 451 
2.4 Mode register 2 for A/D converter (ADM2) ........................................................................................................ 452 
2.5 A/D converter trigger mode register (ADTRG)................................................................................................... 453 
2.6 Analog input channel assignment register (ADS).............................................................................................. 454 
2.7 12-bit A/D conversion result register (ADCR).................................................................................................... 456 
2.8 8-bit A/D conversion result register (ADCRH).................................................................................................... 457 
2.9 Conversion Result Compare Upper Value Setting Register (ADUL) ................................................................. 458 
2.10 Translation Results Compare Lower Limit Settings Register (ADLL) ................................................................ 458 
2.11 A/D Sample Time Control Register (ADNSMP)................................................................................................. 459 