Cmsemicon CMS80F751 Series Bedienungsanleitung

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CMS80F661x 数据手册

CMS80F751x Reference Manual

Enhanced Flash 8-bit 1T 8051- Microcontroller

Rev. 1.05

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 CMS80F751x  Reference  Manual 
Contents
CMS80F751x Reference Manual .............................................................................................1
Contents ...................................................................................................................................2
Central Processing Unit（CPU）...................................................................................13 
1 Reset Vector（0000H）............................................................................................................................................13 
2 BOOT Partition ..........................................................................................................................................................13 
3 Accumulator（ACC）................................................................................................................................................15 
4 B Register（B）........................................................................................................................................................15 
5 Stack Pointer Register（SP）...................................................................................................................................15 
6 Data Pointer Register（DPTR0/DPTR1）.................................................................................................................15 
7 Data Pointer Selection Register（DPS）..................................................................................................................16 
8 Program Status Register（PSW）............................................................................................................................16 
9 Program Counter（PC）...........................................................................................................................................17 
10 Timing Access Register（TA）..................................................................................................................................17 
Memory And Register Map..............................................................................................18 
1 Program Memory FLASH ..........................................................................................................................................18 
2 Non-volatile Data Memory Data FLASH....................................................................................................................19 
3 General Data Register RAM......................................................................................................................................20 
4 General External Data Register XRAM .....................................................................................................................22 
5 Special Function Register Table SFR........................................................................................................................23 
6 External Special Function Register XSFR.................................................................................................................25 
Reset.................................................................................................................................33 
1 Power-On Reset........................................................................................................................................................33 
2 External Reset...........................................................................................................................................................35 
3 LVR Low Voltage Reset.............................................................................................................................................35 
4 Watchdog Reset (WDT) ............................................................................................................................................36 
5 Software Reset..........................................................................................................................................................37 
6 CONFIG Status Protection Reset..............................................................................................................................37 
7 Power-On Configuration Monitoring Reset................................................................................................................37 
Clock Structure ................................................................................................................38 
1 System Clock Structure.............................................................................................................................................38 
2Related registers .......................................................................................................................................................39 
2.1 Oscillator Control Register CLKDIV ......................................................................................................................39 
2.2 System Clock Switch Register SCKSEL ...............................................................................................................39 
2.3 System Clock Status Register SCKSTAU .............................................................................................................40 
2.4 System Clock Monitor Register SCM ....................................................................................................................41 
2.5 Function Clock Control Register............................................................................................................................42 
3 System Clock Switching ............................................................................................................................................44 
4 System Clock Monitoring...........................................................................................................................................45 
Power Management .........................................................................................................46 
1 Power Management Register PCON.........................................................................................................................46 
2 Power Monitoring Register LVDCON ........................................................................................................................47 
3 IDLE Mode ................................................................................................................................................................47 
4 STOP Sleep Mode.....................................................................................................................................................48 

 
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4.1 Sleep And Wake-Up..............................................................................................................................................48 
4.2 Wake Waiting Status .............................................................................................................................................48 
4.3 Sleep And Wake-Up Time .....................................................................................................................................49 
4.4 Reset Operation During Sleep ..............................................................................................................................49 
4.5 Sleep Power Consumption In Debug Mode ..........................................................................................................49 
4.6 Sleep Mode Application Example..........................................................................................................................50 
Interrupt ............................................................................................................................51 
1 Interruption Overview ................................................................................................................................................51 
2 External Interruption ..................................................................................................................................................52 
2.1 INT0/INT1 Interruption ..........................................................................................................................................52 
2.2 GPIO Interruption ..................................................................................................................................................52 
3 Interruption And Wake-Up From Sleep......................................................................................................................52 
4 Interruption Register..................................................................................................................................................53 
4.1 Interruption Mask Register ....................................................................................................................................53 
4.1.1 Interruption Mask Register IE .......................................................................................................................53 
4.1.2 Interruption Mask Register EIE2 ...................................................................................................................54 
4.1.3 Timer2 Interruption Mask Register T2IE .......................................................................................................55 
4.1.4 P0 Port Interrupt Control Register P0EXTIE .................................................................................................55 
4.1.5 P1 Port Interrupt Control Register P1EXTIE .................................................................................................56 
4.1.6 P2 Port Interrupt Control Register P2EXTIE .................................................................................................56 
4.1.7 P5 Port Interrupt Control Register P5EXTIE .................................................................................................56 
4.2 Interrupt Priority Control Register..........................................................................................................................57 
4.2.1 Interrupt Priority Control Register IP .............................................................................................................57 
4.2.2 Interrupt Priority Control Register EIP1.........................................................................................................58 
4.2.3 Interrupt Priority Control Register EIP2.........................................................................................................58 
4.2.4 Interrupt Priority Control Register EIP3.........................................................................................................59 
4.3 Interrupt Flag Bit Register .....................................................................................................................................60 
4.3.1 Timer0/1、INT0/1 Interrupt Flag Bit Register TCON.....................................................................................60 
4.3.2 Timer2 Interrupt Flag Bit Register T2IF.........................................................................................................61 
4.3.3 External Interrupt Flag Bit Register EIF2 ......................................................................................................61 
4.3.4 SPI Interrupt Flag Bit Register SPSR............................................................................................................62 
4.3.5 I2C Master Mode Interrupt Flag Bit Register I2CMCR/I2CMSR ...................................................................63 
4.3.6 I2C Slave Mode Status Register I2CSSR .....................................................................................................63 
4.3.7 UART Control Register SCONn ....................................................................................................................64 
4.3.8 P0 Interrupt Flag Bit Register P0EXTIF ........................................................................................................64 
4.3.9 P1 Interrupt Flag Bit Register P1EXTIF ........................................................................................................64 
4.3.10 P2 Interrupt Flag Bit Register P2EXTIF ....................................................................................................65 
4.3.11 P5 Interrupt Flag Bit Register P5EXTIF ....................................................................................................65 
4.4 Clear Operation Of Interrupt Flag..........................................................................................................................66 
4.5 Special Interrupt Flag Bits In Debug Mode............................................................................................................67 
I/O Port..............................................................................................................................68 
1 GPIO Function...........................................................................................................................................................68 
1.1 PORTx Data Register Px ......................................................................................................................................68 
1.2 PORTx Direction Register PxTRIS........................................................................................................................69 
1.3 PORTx Open Drain Control Register PxOD..........................................................................................................69 
1.4 PORTx Pull-up Resistor Control Register PxUP ...................................................................................................69 
1.5 PORTx Pull-Down Resistor Control Register PxRD..............................................................................................70 
1.6 PORTx Slope Control Register PxSR ...................................................................................................................70 
1.7 PORTx Data Input Selection Register PxDS.........................................................................................................70 
2 Reuse Function .........................................................................................................................................................71 
2.1 Port Reuse Function Table ....................................................................................................................................71 

 
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2.2 Port Reuse Function Configuration Register .........................................................................................................73 
2.3 Port Input Function Allocation Register .................................................................................................................74 
2.4 Communication Input Function Allocation Register ...............................................................................................76 
2.5 External Port Interrupt Control Register ................................................................................................................77 
2.6 Reuse Functions Application Notes.......................................................................................................................78 
Watchdog Timer（WDT）................................................................................................79 
1 Overview ...................................................................................................................................................................79 
2 Related Register........................................................................................................................................................79 
2.1 Watchdog Control Register WDCON ....................................................................................................................79 
2.2 Watchdog Overflow Control Register CKCON ......................................................................................................80 
3 WDT Interrupt............................................................................................................................................................81 
3.1 Interruption Mask Register EIE2 ...........................................................................................................................81 
3.2 Interrupt Priority Control Register EIP2 .................................................................................................................82 
Timer 0/1（Timer0/1）.....................................................................................................83 
1 Overview ...................................................................................................................................................................83 
2 Related Register........................................................................................................................................................84 
2.1 Timer0/1 Mode Register TMOD ............................................................................................................................84 
2.2 Timer0/1 Control Register TCON ..........................................................................................................................85 
2.3 Timer0 Low Bit Data Register TL0 ........................................................................................................................86 
2.4 Timer0 High Bit Data Register TH0 .......................................................................................................................86 
2.5 Timer1 Low Bit Data Register TL1 ........................................................................................................................86 
2.6 Timer1 High Bit Data Register TH1 .......................................................................................................................86 
2.7 Function Clock Control Register CKCON..............................................................................................................87 
3 Timer0/1 Interrupt......................................................................................................................................................88 
3.1 Interruption Mask Register IE................................................................................................................................88 
3.2 Interrupt Priority Control Register IP .....................................................................................................................89 
3.3 Timer0/1、INT0/1 Interrupt Flag Register TCON ..................................................................................................90 
4 Timer0 Operating Mode.............................................................................................................................................91 
4.1 T0 -Mode0（13-Bit Timing/Counting Mode）........................................................................................................91 
4.2 T0 -Mode1（16-Bit Timing/Counting Mode）........................................................................................................91 
4.3 T0 -Mode2（8-Bit Auto Reload Timing/Counting Mode）.....................................................................................92 
4.4 T0 -Mode3（Two Separate 8-Bit Timer/Counters）..............................................................................................93 
5 Timer1 Operating Mode.............................................................................................................................................94 
5.1 T1 -Mode0（13-Bit Timing/Counting Mode）........................................................................................................94 
5.2 T1 -Mode1（16-Bit Timing/Counting Mode）........................................................................................................94 
5.3 T1 -Mode2（8-Bit Auto Reload Timing/Counting Mode）.....................................................................................95 
5.4 T1 -Mode3（Stop Counting）...............................................................................................................................95 
Timer 2（Timer2）...........................................................................................................96 
1 Overview ...................................................................................................................................................................96 
2 Related Register........................................................................................................................................................97 
2.1 Timer2 Control Register T2CON ...........................................................................................................................97 
2.2 Timer2 Low Bit Data Register TL2 ........................................................................................................................98 
2.3 Timer2 High Bit Data Register TH2 .......................................................................................................................98 
2.4 Timer2 Compare/Capture/Reload Register Low 8-Bit RLDL .................................................................................98 
2.5 Timer2 Compare/Capture/Reload Register High 8-Bit RLDH................................................................................98 
2.6 Timer2 Compare/Capture Channel1 Register Low 8-Bit CCL1 .............................................................................99 

 
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2.7 Timer2 Compare/Capture Channel1 Register High 8-Bit CCH1............................................................................99 
2.8 Timer2 Compare/Capture Channel2 Register Low 8-Bit CCL2 .............................................................................99 
2.9 Timer2 Compare/Capture Channel2 Register High 8-Bit CCH2............................................................................99 
2.10 Timer2 Compare/Capture Channel3 Register Low 8-Bit CCL3 .............................................................................99 
2.11 Timer2 Compare/Capture Channel3 Register High 8-Bit CCH3..........................................................................100 
2.12 Timer2 Compare Capture Control Register CCEN..............................................................................................100 
3 Timer2 Interrupt.......................................................................................................................................................101 
3.1 Interrupt Related Register ...................................................................................................................................101 
3.1.1 Interrupt Mask Register IE ......................................................................................................................101 
3.1.2 Timer2 Interrupt Mask Register T2IE ......................................................................................................102 
3.1.3 Interrupt Priority Control Register IP .......................................................................................................103 
3.1.4 Timer2 Interrupt Flag Register T2IF........................................................................................................104 
3.2 Timer Interrupt.....................................................................................................................................................105 
3.3 External Trigger Interrupt ....................................................................................................................................105 
3.4 Compare Interrupt ...............................................................................................................................................105 
3.5 Capture Interrupt .................................................................................................................................................105 
4 Timer2 Function Description....................................................................................................................................106 
4.1 Timing Mode .......................................................................................................................................................106 
4.2 Reload Mode.......................................................................................................................................................106 
4.3 Gate Control Timing Mode ..................................................................................................................................107 
4.4 Event Counting Mode..........................................................................................................................................107 
4.5 Compare Mode ...................................................................................................................................................107 
4.5.1 Compare Mode0 .....................................................................................................................................108 
4.5.2 Compare Mode1.....................................................................................................................................109 
4.6 Capture Mode .....................................................................................................................................................110 
4.6.1 Capture Mode0.......................................................................................................................................110 
4.6.2 Capture Mode1....................................................................................................................................... 111 
Timer 3/4（Timer3/4）................................................................................................... 112 
1 Overview .................................................................................................................................................................112 
2 Related Register......................................................................................................................................................113 
2.1 Timer3/4 Control Register T34MOD....................................................................................................................113 
2.2 Timer3 Low Bit Data Register TL3 ......................................................................................................................113 
2.3 Timer3 High Bit Data Register TH3 .....................................................................................................................114 
2.4 Timer4 Low Bit Data Register TL4 ......................................................................................................................114 
2.5 Timer4 High Bit Data Register TH4 .....................................................................................................................114 
3 Timer3/4 Interrupt....................................................................................................................................................115 
3.1 Interrupt Mask Register EIE2 ..............................................................................................................................115 
3.2 Interrupt Priority Control Register EIP2 ...............................................................................................................116 
3.3 External Interrupt Flag Bit Register EIF2.............................................................................................................117 
4 Timer3 Operation Mode...........................................................................................................................................118 
4.1 T3 -Mode0（13-Bit Timing Mode）.....................................................................................................................118 
4.2 T3 -Mode1（16-Bit Timing Mode）.....................................................................................................................118 
4.3 T3 -Mode2（8-Bit Auto Reload Timing Mode）..................................................................................................119 
4.4 T3 -Mode3（Two Separate 8-Bit Timer）...........................................................................................................120 
5 Timer4 Operation Mode...........................................................................................................................................121 
5.1 T4 -Mode0（13-Bit Timing Mode）.....................................................................................................................121 
5.2 T4 -Mode1（16-Bit Timing Mode）.....................................................................................................................121 
5.3 T4- Mode2（8-Bit Auto Reload Timing Mode）..................................................................................................122 
5.4 T4- Mode3（Stop Counting）.............................................................................................................................122 

 
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LSE_Timer ......................................................................................................................123 
1 Overview .................................................................................................................................................................123 
2 Related Registers....................................................................................................................................................123 
2.1 LSE Timer Data Register Low 8-bit LSECRL ......................................................................................................123 
2.2 LSE Timer Data Register High 8-bit LSECRH.....................................................................................................123 
2.3 LSE Timer Control Register LSECON .................................................................................................................124 
3 Interrupt And Sleep Wake-up ..................................................................................................................................125 
4 Function Description................................................................................................................................................125 
Wake-Up Timer（WUT）................................................................................................126 
1 Overview .................................................................................................................................................................126 
2 Related Registers....................................................................................................................................................126 
2.1 WUTCRH Register..............................................................................................................................................126 
2.2 WUTCRL Register...............................................................................................................................................126 
3 Function Description................................................................................................................................................127 
Baud Rate Timer（BRT）..............................................................................................128 
1 Overview .................................................................................................................................................................128 
2 Related Registers....................................................................................................................................................128 
2.1 BRT Module Control Register BRTCON .............................................................................................................128 
2.2 BRT Timer Data Is Loading The Low 8-bit Register BRTDL................................................................................128 
2.3 BRT Timer Data Is Loading The High 8-bit Register BRTDH ..............................................................................129 
3 Function Description................................................................................................................................................129 
Cycle Redundancy Check（CRC）..............................................................................130 
1 Overview .................................................................................................................................................................130 
2 Related Registers....................................................................................................................................................130 
2.1 CRC Data Input Register CRCIN ........................................................................................................................130 
2.2 CRC Operation Result Low 8-bit Data Register CRCDL.....................................................................................130 
2.3 CRC Operation Result High 8-bit Data Register CRCDH ...................................................................................130 
3 Function Description................................................................................................................................................131 
Multiplication/Division Unit（MDU）............................................................................132 
1 Overview .................................................................................................................................................................132 
2 Related Registers....................................................................................................................................................132 
2.1 Operation Register MD0 .....................................................................................................................................133 
2.2 Operation Register MD1 .....................................................................................................................................133 
2.3 Operation Register MD2 .....................................................................................................................................134 
2.4 Operation Register MD3 .....................................................................................................................................134 
2.5 Operation Register MD4 .....................................................................................................................................134 
2.6 Operation Register MD5 .....................................................................................................................................135 
2.7 Operation Register ARCON ................................................................................................................................135 
3 Function Description................................................................................................................................................136 
3.1 32bit/16bit Division Operation .............................................................................................................................137 
3.2 16bit/16bit Division Operation .............................................................................................................................137 
3.3 16bit*16bit Multiplication Operation.....................................................................................................................138 
3.4 32bit Shift Operation ...........................................................................................................................................138 
3.5 32bit Normalization Operation.............................................................................................................................139 
BUZZER ..........................................................................................................................140 
1 Overview .................................................................................................................................................................140 
2 Related Registers....................................................................................................................................................140 

 
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2.1 BUZZER Control Register BUZCON...................................................................................................................140 
2.2 BUZZER Frequency Control Register BUZDIV ...................................................................................................140 
3 Function Description................................................................................................................................................141 
Enhanced PWM Module ................................................................................................142 
1 Overview .................................................................................................................................................................142 
2 Characteristic ..........................................................................................................................................................142 
3 Pin Configuration.....................................................................................................................................................143 
4 Function Description................................................................................................................................................143 
4.1 Functional Diagram .............................................................................................................................................143 
4.2 Edge-aligned .......................................................................................................................................................144 
4.3 Center-aligned.....................................................................................................................................................145 
4.3.1 Symmetric counting ................................................................................................................................145 
4.3.2 Asymmetric counting ..............................................................................................................................146 
4.4 Complementary Mode.........................................................................................................................................148 
4.5 Synchronize Mode ..............................................................................................................................................149 
4.6 Mask Output........................................................................................................................................................149 
4.7 Brake Function ....................................................................................................................................................149 
5 PWM Related Registers ..........................................................................................................................................150 
5.1 PWM Control Register PWMCON.......................................................................................................................150 
5.2 PWM Output Enable Control Register PWMOE..................................................................................................150 
5.3 PWM0/1 Clock Prescaler Control Register PWM01PSC ....................................................................................151 
5.4 PWM2/3 Clock Prescaler Control Register PWM23PSC ....................................................................................151 
5.5 PWM4/5 Clock Prescaler Control Register PWM45PSC ....................................................................................152 
5.6 PWM Clock Division Control Register PWMnDIV(n=0-5)....................................................................................152 
5.7 PWM Data load Enable Control Register PWMLOADEN....................................................................................152 
5.8 PWM Output Polarity Control Register PWMPINV..............................................................................................153 
5.9 PWM Counter Mode Control Register PWMCNTM.............................................................................................153 
5.10 PWM Counter Enable Control Register PWMCNTE ...........................................................................................153 
5.11 PWM Counter Mode Control Register PWMCNTCLR.........................................................................................154 
5.12 PWM Period Data Low 8-bit Register PWMPnL (n=0-5) .....................................................................................154 
5.13 PWM Period Data High 8-bit Register PWMPnH (n=0-5)....................................................................................154 
5.14 PWM Compare Data Low 8-bit Register PWMDnL (n=0-5).................................................................................154 
5.15 PWM Compare Data High 8-bit Register PWMDnH (n=0-5) ...............................................................................155 
5.16 PWM Compare Data Low 8-bit Registers Down PWMDDnL (n=0-5) ..................................................................155 
5.17 PWM Compare Data High 8-bit Registers Down PWMDDnH (n=0-5).................................................................155 
5.18 PWM Dead Zone Enable Control Register PWMDTE.........................................................................................155 
5.19 PWM0/1 Dead Zone Delay Data Register PWM01DT ........................................................................................156 
5.20 PWM2/3 Dead Zone Delay Data Register PWM23DT ........................................................................................156 
5.21 PWM4/5 Dead Zone Delay Data Register PWM45DT ........................................................................................156 
5.22 PWM Mask Control Register PWMMASKE.........................................................................................................156 
5.23 PWM Mask Data Register PWMMASKD.............................................................................................................157 
5.24 PWM Brake Control Register PWMFBKC...........................................................................................................157 
5.25 PWM Brake Data Register PWMFBKD...............................................................................................................158 
6 PWM Interrupt .........................................................................................................................................................159 
6.1 Interruption Mask Register EIE2 .........................................................................................................................159 
6.2 Interrupt Priority Control Register EIP2 ...............................................................................................................160 
6.3 PWM Period Interrupt Mask Register PWMPIE ..................................................................................................160 
6.4 PWM Zero Interrupt Mask Register PWMZIE......................................................................................................161 
6.5 PWM Up Compare Interrupt Mask Register PWMUIE ........................................................................................161 
6.6 PWM Down Compare Interrupt Mask Register PWMDIE....................................................................................161 
6.7 PWM Period Interrupt Flag Register PWMPIF ....................................................................................................161 
6.8 PWM Zero Interrupt Flag Register PWMZIF .......................................................................................................162 

 
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6.9 PWM Up Compare Interrupt Flag Register PWMUIF ..........................................................................................162 
6.10 PWM Down Compare Interrupt Flag Register PWMDIF .....................................................................................162
Hardware LCD Driver.....................................................................................................163 
1 Overview .................................................................................................................................................................163 
2 Characteristic ..........................................................................................................................................................163 
3 Related Register......................................................................................................................................................164 
3.1 LCD Control Register LCDCON0 ........................................................................................................................164 
3.2 LCD Control Register LCDCON1 ........................................................................................................................165 
3.3 LCD Control Register LCDCON2 ........................................................................................................................165 
3.4 LCD Control Register LCDCON3 ........................................................................................................................166 
3.5 COM Port Enable Control Register LCDCOMEN................................................................................................166 
3.6 SEG Port Enable Control Register LCDSEGEN0 ...............................................................................................167 
3.7 SEG Port Enable Control Register LCDSEGEN1 ...............................................................................................167 
3.8 SEG Port Enable Control Register LCDSEGEN2 ...............................................................................................167 
3.9 SEG Data Register 6(n=0-19) .............................................................................................................................167 
4 COM -SEG data-sheet ............................................................................................................................................168 
4.1 1/4DUTY .............................................................................................................................................................168 
4.2 1/5DUTY .............................................................................................................................................................169 
4.3 1/6DUTY .............................................................................................................................................................170 
4.4 1/8DUTY .............................................................................................................................................................171 
Hardware LED Driver.....................................................................................................172 
1 Overview .................................................................................................................................................................172 
2 Characteristic ..........................................................................................................................................................172 
3 Related Register......................................................................................................................................................172 
3.1 LED Control Register LEDCON ..........................................................................................................................172 
3.2 LED Clock Prescaler Data Register Low 8-bit LEDCLKL....................................................................................173 
3.3 LED Clock Prescaler Data Register High 8-bit LEDCLKH ..................................................................................173 
3.4 COM Port Effective Time Selection Register LEDCOMTIME..............................................................................173 
3.5 COM Port Enable Control Register LEDCOMEN ................................................................................................174 
3.6 SEG Port Enable Control Register LEDSEGEN0................................................................................................174 
3.7 SEG Port Enable Control Register LEDSEGEN1................................................................................................174 
3.8 SEG Port Enable Control Register LEDSEGEN2................................................................................................174 
3.9 COM0 Corresponds To SEG Data Register LEDC0DATAn（n=0-2）................................................................175 
3.10 COM1 Corresponds To SEG Data Register LEDC1DATAn（n=0-2）................................................................175 
3.11 COM2 Corresponds To SEG Data Register LEDC2DATAn（n=0-2）................................................................176 
3.12 COM3 Corresponds To SEG Data Register LEDC3DATAn（n=0-2）................................................................176 
3.13 COM4 Corresponds To SEG Data Register LEDC4DATAn（n=0-2）................................................................177 
3.14 COM5 Corresponds To SEG Data Register LEDC5DATAn（n=0-2）................................................................177 
3.15 COM6 Corresponds To SEG Data Register LEDC6DATAn（n=0-2）................................................................178 
3.16 COM7 Corresponds To SEG Data Register LEDC7DATAn（n=0-2）................................................................178 
3.17 SEG Port P04-P07 Drive Current Control Register LEDSDRP0H.......................................................................179 
3.18 SEG Port P10-P13 Drive Current Control Register LEDSDRP1L .......................................................................179 
3.19 SEG Port P14-P17 Drive Current Control Register LEDSDRP1H.......................................................................180 
3.20 SEG Port P20-P23 Drive Current Control Register LEDSDRP2L .......................................................................180 
3.21 SEG Port P24-P27 Drive Current Control Register LEDSDRP2H.......................................................................181 
3.22 COM Port Current Sink Selection Register P0DR...............................................................................................182 
4 LED Driver Output Waveform..................................................................................................................................183 
SPI...................................................................................................................................184 

 
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1 Overview .................................................................................................................................................................184 
2 SPI Port Configuration.............................................................................................................................................185 
3 SPI Hardware Description .......................................................................................................................................186 
4 SPI Related Register...............................................................................................................................................187 
4.1 SPI Control Register SPCR.................................................................................................................................187 
4.2 SPI Data Register SPDR ....................................................................................................................................188 
4.3 Slave Select Control Register SSCR ..................................................................................................................188 
4.4 SPI State Register SPSR ....................................................................................................................................189 
5 SPI Master Model....................................................................................................................................................190 
5.1 Write Collision Error ............................................................................................................................................191 
6 SPI Slave Mode.......................................................................................................................................................192 
6.1 Addressed Error ..................................................................................................................................................192 
6.2 Write Collision Error ............................................................................................................................................192 
7 SPI Clock Control Logic ..........................................................................................................................................194 
7.1 SPI Clock Phase And Polarity Control.................................................................................................................194 
7.2 SPI Transport Format..........................................................................................................................................194 
7.3 CPHA=0 Transport Format..................................................................................................................................194 
7.4 CPHA=1 Transport Format..................................................................................................................................195 
8 SPI Data Transmission............................................................................................................................................196 
8.1 SPI Transfer Start................................................................................................................................................196 
8.2 SPI Transfer End.................................................................................................................................................196 
9 SPI Timing Diagram ................................................................................................................................................197 
9.1 Master Mode Transmission .................................................................................................................................197 
9.2 Slave Mode Transmission ...................................................................................................................................197 
10 SPI Interrupt ............................................................................................................................................................198 
10.1 Interrupt Mask Register EIE2 ..............................................................................................................................198 
10.2 Interrupt Priority Control Register EIP2 ...............................................................................................................199 
10.3 Peripheral Interrupt Flag Register EIF2...............................................................................................................200 
I2C Module ......................................................................................................................201 
1 Overview .................................................................................................................................................................201 
2 I2C Port Configuration..............................................................................................................................................202 
3 I2C Master Mode .....................................................................................................................................................202 
3.1 I2C Period Timer Register In Master Mode..........................................................................................................203 
3.2 I2C Control And Status Register In Master Mode ................................................................................................203 
3.3 I2C Slave Address Register .................................................................................................................................206 
3.4 Sending And Receiving Data Register In I2C Master Control Mode ....................................................................206 
4 I2C Slave Mode .......................................................................................................................................................207 
4.1 I2C Own Address Register I2CSADR ..................................................................................................................207 
4.2 I2C Control Register And Status Register Of I2C Slave Mode I2CSCR/I2CSSR .................................................207 
4.3 Sending And Receiving Cached Register Of I2C Slave Mode I2CSBUF.............................................................208 
5 I2C interrupt .............................................................................................................................................................209 
5.1 Interrupt Mask Register EIE2 ..............................................................................................................................209 
5.2 Interrupt Priority Control Register EIP2 ...............................................................................................................210 
5.3 Peripheral Interrupt Flag Register EIF2...............................................................................................................211 
6 I2C Transmission Method of Slave Mode.................................................................................................................212 
6.1 Single Receiving .................................................................................................................................................212 
6.2 Single Sending ....................................................................................................................................................212 
6.3 Continuous Receiving .........................................................................................................................................213 
6.4 Continuous Sending............................................................................................................................................213 
UARTn Moudle ...............................................................................................................214 
1 Overview .................................................................................................................................................................214 

 
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2 UARTn Port Configuration.......................................................................................................................................214 
3 UARTn Baud Rate...................................................................................................................................................215 
3.1 Baud Rate Clock Source .....................................................................................................................................215 
3.2 Baud Rate Calculation ........................................................................................................................................215 
3.3 Baud Rate Deviation ...........................................................................................................................................216 
4 UARTn Registers ....................................................................................................................................................218 
4.1 UART0/1 Baud Rate Selection Register FUNCCR .............................................................................................218 
4.2 UARTn Buffer Register SBUFn ...........................................................................................................................218 
4.3 UART Control Register SCONn ..........................................................................................................................219 
4.4 PCON Register ...................................................................................................................................................220 
5 UARTn Interrupt ......................................................................................................................................................221 
5.1 Interrupt Mask Register IE...................................................................................................................................221 
5.2 Interrupt Priority Control Register IP ...................................................................................................................222 
5.3 Interrupt Priority Control Register EIP3 ...............................................................................................................223 
6 UARTn Mode...........................................................................................................................................................224 
6.1 Mode 0 - Synchronous Mode..............................................................................................................................224 
6.2 Mode 1 - 8-bit Asynchronous Mode (Variable Baud Rate)..................................................................................224 
6.3 Mode 2 - 9-bit Asynchronous Mode (Fixed Baud Rate) ......................................................................................225 
6.4 Mode 3 - 9-bit Asynchronous Mode (Variable Baud Rate)..................................................................................225 
Analog To Digital Conversion (ADC)............................................................................226 
1 Overview .................................................................................................................................................................226 
2 ADC Configuration ..................................................................................................................................................227 
2.1 Port Configuration ...............................................................................................................................................227 
2.2 Channel Selection ...............................................................................................................................................227 
2.3 ADC Reference Voltage ......................................................................................................................................227 
2.4 Conversion Clock ................................................................................................................................................228 
2.5 Result Formatting................................................................................................................................................228 
3 ADC Hardware Triggered Start................................................................................................................................229 
3.1 External Port Edge Trigger ADC..........................................................................................................................229 
3.2 PWM Triggered ADC...........................................................................................................................................229 
3.3 Hardware Trigger Delay Before Starting .............................................................................................................229 
4 ADC Results Of Comparison...................................................................................................................................230 
5 ADC Working Principle............................................................................................................................................230 
5.1 Start Conversion .................................................................................................................................................230 
5.2 Complete Conversion..........................................................................................................................................230 
5.3 Terminate Conversion .........................................................................................................................................230 
5.4 A/D Conversion Step...........................................................................................................................................231 
5.5 Enter Sleep Mode During Conversion.................................................................................................................231 
6 Related Register......................................................................................................................................................232 
6.1 AD Control Register ADCON0.............................................................................................................................232 
6.2 AD Control Register ADCON1.............................................................................................................................233 
6.3 AD Control Register ADCON2.............................................................................................................................233 
6.4 AD Channel Selection Register ADCCHS ...........................................................................................................234 
6.5 AD Comparator Control Register ADCMPC ........................................................................................................234 
6.6 AD Hardware Trigger Delay Data Register ADDLYL ...........................................................................................235 
6.7 AD Data Register High Bits ADRESH，ADFM=0(Left-aligned) ..........................................................................235 
6.8 AD Data Register Low Bits ADRESL，ADFM=0(Left-aligned)............................................................................235 
6.9 AD Data Register High ADRESH，ADFM=1(Right-aligned) ...............................................................................236 
6.10 AD Data Register Low ADRESH，ADFM=1(Right-aligned)................................................................................236 
6.11 AD Comparator Data Register ADCMPH ............................................................................................................236 