Cmsemicon CMS32H6157 Bedienungsanleitung

CMS32H6157 User Manual

Ultra-low-power 32-bit measurement SOC based on the ARM® Cortex®-M0+

Rev. 0.1.1

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Rev.0.1.1

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Document Instructions

This manual is the user manual for the CMS32H6157 microcontroller product. The user manual is the application

instruction material on how to use this series of products, including the structure, function description, working mode

and register configuration of each functional module. Each function module is introduced in a special section.

The user manual is a description of all functional modules of this series of products. If you want to know the

feature description of the specific product (that is, the functional configuration), you can refer to the respective data

sheet.

The data sheet information is as follows::

CMS32H6157datasheet_vx.x.x pdf

Usually in the early stage of chip selection, you shall first check the data sheet to evaluate whether the product

can meet the functional requirements of the design. After basically selecting the required product, you need to check

the user manual to determine whether the working mode of each functional module does meet the requirement. When

determining the selection and entering the programming design stage, you need to read the user manual in detail to

understand the specific implementation and register configuration of each function. Refer to the datasheet for

information on voltages, currents, drive capabilities and pin assignments when designing the hardware.

For a detailed description of the ARM M0+ core, SysTick timer and NVIC, please refer to the respective ARM

documents.

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Contents 
Document Instructions........................................................................................................................................2 
 CPU................................................................................................................19 
 Overview .......................................................................................................................................19 
 Cortex-M0+ core features.............................................................................................................19 
 Debugging features.......................................................................................................................19 
 SWD interface pins .......................................................................................................................21 
 ARM reference document.............................................................................................................22 
 PORT FUNCTION..........................................................................................23
 Port general function.....................................................................................................................23 
 Port multiplexing function..............................................................................................................24 
 Registers for controlling port functions .........................................................................................27 
 Port output control register (PMxx)........................................................................................29 
 Port register (Pxx)..................................................................................................................30 
 Port set control register (PSETxx).........................................................................................31 
 Port clear control register (PCLRxx)......................................................................................32 
 Pull-up resistor selection register (PUxx) ..............................................................................33 
 Pull-down resistor selection register (PDxx)..........................................................................34 
 Port output mode register (POMxx).......................................................................................35 
 Port mode control register (PMCxx)......................................................................................36 
 Port readback register (PREADxx)........................................................................................37 
 Port multiplexing function configuration register (PxxCFG) ..................................................38 
 External interrupt port selection register (INTPnPCFG)........................................................41 
 External reset port mask register (RSTM).............................................................................44 
 Handling of unused ports..............................................................................................................45 
 Register settings when using the multiplexing function................................................................46 
Basic ideas when using multiplexing functions ...................................................................................46 
 SYSTEM STRUCTURE .................................................................................65
 Overview .......................................................................................................................................65 
 System address division...............................................................................................................66 
 Peripheral address assignment....................................................................................................67 
 CLOCK GENERATION CIRCUIT..................................................................68 
 Function of clock generation circuit ..............................................................................................68 
 Structure of clock generation circuit..............................................................................................70 
 Registers for controlling clock generation circuit..........................................................................73 
 Clock operation mode control register (CMC).......................................................................73 
 System clock control register (CKC)......................................................................................75 
 Clock operation status control register (CSC).......................................................................76 
 Status register of the oscillation stabilization time counter (OSTC)......................................78 

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 Oscillation stabilization time selection register (OSTS).........................................................80 
 Peripheral enabled registers 0, 1 (PER0, PER1)..................................................................82 
 Subsystem clock supply mode control register (OSMC).......................................................85 
 High-speed internal oscillator frequency selection register (HOCODIV) ..............................86 
 High-speed internal oscillator trim register (HIOTRM) ..........................................................87 
 Subsystem clock selection register (SUBCKSEL).................................................................88 
 System clock oscillation circuit......................................................................................................89 
 X1 oscillation circuit ...............................................................................................................89 
 XT1 oscillation circuit.............................................................................................................90 
 High-speed internal oscillator ................................................................................................93 
 Low-speed internal oscillator.................................................................................................93 
 Operation of clock generation circuit ............................................................................................94 
 Clock control .................................................................................................................................96 
 Example of setting up a high-speed internal oscillator..........................................................96 
 Example of setting X1 oscillation circuit ................................................................................98 
 Example of setting XT1 oscillation circuit..............................................................................99 
 CPU clock state transition diagram......................................................................................100 
 Conditions before CPU clock transfer and post-transfer processing..................................106 
 Time required to switch CPU clock and main system clock................................................108 
 Conditions before clock oscillation stops.............................................................................109 
 High-speed internal oscillation correction...................................................................................110 
 High-speed internal oscillation self-adjustment function .....................................................110 
 Register description.............................................................................................................111 
 High-speed internal oscillation frequency correction control register (HOCOFC)...........111 
 Action description.................................................................................................................113 
 Action summary................................................................................................................113 
 Action setting flow............................................................................................................116 
 Notes on use........................................................................................................................117 
 SFR Access......................................................................................................................117 
 Actions on resetting..........................................................................................................117 
 Oscillation stop detection circuit .................................................................................................118 
 Composition of the oscillation-stop detection circuit............................................................118 
 The registers used by the oscillation-stop detection circuit.................................................119 
 Peripheral enabled Register 1(PER1) .............................................................................119 
 Oscillation stop detection control register (SCMCTL)......................................................119 
 Oscillation stop detection mode register (SCMMD).........................................................120 
 Oscillation stop detection status register (SCMST).........................................................120 
 Operation of oscillation stop detection circuit......................................................................121 
 Operation method of oscillation stop detection circuit.....................................................121 

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 Operation of oscillation stop detection circuit in deep sleep mode.....................................122 
 Notes on the oscillation stop detection function ..................................................................122 
 GENERAL-PURPOSE TIMER UNIT TIMER8 .............................................123 
 General-purpose timer unit functions..........................................................................................125 
 Independent channel operation functions............................................................................125 
 Multi-channel linkage operation functions ...........................................................................127 
 LIN-bus support function (channel 3 only)...........................................................................129 
 Structure of the general-purpose timer unit................................................................................130 
 General-purpose timer unit register list ...............................................................................132 
 Timer count register mn (TCRmn).......................................................................................133 
 Timer data register mn (TDRmn).........................................................................................135 
 Registers that control the general-purpose timer unit ................................................................136 
 Peripheral enable register 0(PER0).....................................................................................137 
 Timer clock selection register m (TPSm).............................................................................138 
 Timer mode register mn (TMRmn) ......................................................................................141 
 Timer status register mn (TSRmn)......................................................................................145 
 Timer channel enable status register m (TEm) ...................................................................146 
 Timer channel start register m (TSm)..................................................................................147 
 Timer channel stop register m (TPSm)................................................................................148 
 Timer input output selection register (TIOS0)......................................................................149 
 Timer output enable register m (TOEm)..............................................................................150 
 Timer output register m (TOm)............................................................................................151 
 Timer output level register m (TOLm)..................................................................................152 
 Timer output mode register m (TOMm)...............................................................................153 
 Input switching control register (ISC)...................................................................................154 
 Noise filter enable register (NFEN1)....................................................................................155 
 Registers for controlling timer input/output pin port functions.............................................156 
 Basic rules of the general-purpose timer unit.............................................................................157 
 Basic rules of multi-channel linkage operation function......................................................157 
 Timer channel start register m (TSm)..................................................................................160 
 Operation of counters .................................................................................................................161 
 Counting clock (FTCLK)..........................................................................................................161 
 Start timing of counter..........................................................................................................163 
 Operation of counters ..........................................................................................................164 
 Control of channel outputs (TOmn pins).....................................................................................169 
 Block diagram of the TOmn pin output circuit......................................................................169 
 Settings of the TOmn pin output..........................................................................................170 
 Cautions for channel output operation.................................................................................171 
 One-time operation of TOmn bit..........................................................................................176 

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 Timer interrupt and TOmn pin output when counting starts................................................177 
 Control of Timer Input (TImn)......................................................................................................178 
 Block diagram of the TImn pin input circuit..........................................................................178 
 Noise filter............................................................................................................................178 
 Cautions for channel input operation...................................................................................179 
 Independent channel operation function for general purpose timer units..................................180 
 Operation as interval timer/square wave output..................................................................180 
 Operation as external event counter....................................................................................184 
 Operation as frequency divider............................................................................................187 
 Operation as input pulse interval measurement..................................................................190 
 Operation as input signal high and low level width measurement......................................194 
 Operation as delay counter..................................................................................................198 
 Multi-channel linkage operation function for general purpose timer units..................................201 
 Operation as single trigger pulse output function................................................................201 
 Operation as PWM function.................................................................................................208 
 Operation as multiple PWM output function........................................................................215 
 Cautions when using the general-purpose timer unit.................................................................224 
 Cautions when using timer output .......................................................................................224 
 TIMERA .......................................................................................................225 
 TimerA function...........................................................................................................................225 
 Structure of Timer A....................................................................................................................226 
 Registers for controlling Timer A.................................................................................................227 
 Peripheral enable register 0(PER0).....................................................................................228 
 Subsystem Clock Supply Mode Control Register (OSMC) .................................................229 
 Timer A count register 0 (TA0) ............................................................................................230 
 Timer A control register 0 (TACR0).....................................................................................231 
 Timer AI/O control register 0 (TAIOC0)...............................................................................232 
 Timer A control register 0 (TAMR0).....................................................................................234 
 Timer A event pin selection register 0 (TAISR0).................................................................235 
 Timer A operation........................................................................................................................236 
 Rewriting the reload register and counter............................................................................236 
 Timer mode..........................................................................................................................237 
 Pulse output mode...............................................................................................................238 
 Event counter mode.............................................................................................................239 
 Pulse width measurement mode .........................................................................................241 
 Pulse period measurement mode........................................................................................242 
 Collaboration with EVENTC.................................................................................................243 
 Output settings for each mode.............................................................................................244 
 Cautions when using timer A......................................................................................................245 

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 Start and stop control of counting........................................................................................245 
 Flag access (TEDGF bit and TUNDF bit of TACR0 register)..............................................245 
 Access to counting registers................................................................................................246 
 Change in mode...................................................................................................................246 
 Setting procedure for TAO pin and TAIO pin.......................................................................246 
 When timer A is not used.....................................................................................................247 
 Stop of timer A operation clock............................................................................................247 
 Setting steps for deep sleep mode (event counter mode)...................................................247 
 Function limitations in deep sleep mode (event counter mode only)..................................248 
 Forced count stop via the TSTOP bit...................................................................................248 
 Digital Filters ........................................................................................................................248 
 Selecting FIL as the count source........................................................................................249 
 REAL TIME CLOCK....................................................................................250 
 Functions of real-time clock........................................................................................................250 
 Structure of real-time clock.........................................................................................................250 
 Registers for controlling real-time clock......................................................................................252 
 Peripheral enable register 0 (PER0)....................................................................................253 
 Real-time clock selection register (RTCCL) ........................................................................254 
 Real-time clock control register 0 (RTCC0).........................................................................255 
 Real-time clock control register 1 (RTCC1).........................................................................256 
 Watch error correction register (SUBCUD) .........................................................................258 
 Second count register (SEC)...............................................................................................259 
 Minute count register (MIN).................................................................................................260 
 Hour count register (HOUR)................................................................................................261 
 Day count register (DAY).....................................................................................................263 
 Week count register (WEEK)...............................................................................................264 
 Month count register (MONTH) ...........................................................................................265 
 Year count register (YEAR).................................................................................................266 
 Alarm minute register (ALARMWM) ....................................................................................267 
 Alarm hour register (ALARMWH) ........................................................................................268 
 Alarm week register (ALARMWW) ......................................................................................269 
 Starting operation of real-time clock....................................................................................270 
 Shifting to sleep mode after starting operation....................................................................271 
 Reading/writing real-time clock............................................................................................272 
 Setting alarm of real-time clock ...........................................................................................274 
 1 Hz output of real-time clock..............................................................................................275 
 Example of watch error correction of real-time clock ..........................................................276 
 15-BIT INTERVAL TIMER ...........................................................................278 
 Functions of 15-bit Interval Timer...............................................................................................278 

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 Structure of 15-bit Interval Timer................................................................................................278 
 Registers controlling 15-bit Interval Timer..................................................................................279 
 Peripheral enable register 0 (PER0)....................................................................................279 
 Real-time clock selection register (RTCCL) ........................................................................280 
 15-bit interval timer control register (ITMC).........................................................................281 
 15-bit interval timer operation .....................................................................................................282 
 15-bit interval timer operation timing....................................................................................282 
 Start of count operation and re-enter to sleep mode after returned from sleep mode........283 
 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER................................284
 Functions of clock output/buzzer output controller.....................................................................284 
 Registers for controlling clock output/buzzer output controller...................................................286 
 Clock output select registers n (CKSn)................................................................................286 
 Operations of clock output/buzzer output controller...................................................................288 
 Cautions of clock output/buzzer output controller.......................................................................288 
 WATCH DOG TIMER...................................................................................289
 Functions of watchdog timer.......................................................................................................289 
 Structure of watch dog timer.......................................................................................................289 
 Registers for controlling watchdog timer.....................................................................................291 
 Watchdog timer enable register (WDTE).............................................................................291 
 LOCKUP control register (LOCKCTL)and its protection register(PRCR) ...........................292 
 WDTCFG configuration registers (WDTCFG0/1/2/3)..........................................................293 
 Operation of watchdog timer.......................................................................................................294 
 Operational control of watchdog timer.................................................................................294 
 Setting overflow time of watchdog timer..............................................................................296 
 Setting window open period of watchdog timer...................................................................297 
 Setting watchdog timer interval interrupt.............................................................................298 
 Operation of the watchdog timer during LOCKUP...........................................................298 
 Operation of the watchdog timer without WDTCFG configured......................................298 
 AD CONVERTER.........................................................................................299 
 Function of A/D converter...........................................................................................................299 
 Registers for controlling A/D converter.......................................................................................301 
 Peripheral enable register (PER1).......................................................................................302
 A/D converter mode register 0 (ADM0)...............................................................................303 
 A/D converter mode register 1 (ADM1)...............................................................................304 
 A/D converter mode register 2 (ADM2)...............................................................................305 
 A/D converter trigger mode register (ADTRG)....................................................................306 
 Analog input channel specification register (ADS)..............................................................307 
 12-bit A/D conversion result register (ADCR)......................................................................310 
 8-bit A/D conversion result register (ADCRH).....................................................................311 

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 Conversion result comparison upper limit setting register (ADUL).....................................311 
 Conversion result comparison lower limit setting register (ADLL)...................................312 
 A/D converter sampling time control register (ADNSMP)................................................313 
 A/D converter sampling time extension control register (ADSMPWAIT).........................315 
 A/D test register (ADTES)................................................................................................316 
 A/D converters charge-discharge control register (ADNDIS)..........................................317 
 Input voltage and conversion result............................................................................................318 
 Operation mode of A/D converter...............................................................................................319 
 Software trigger mode (select mode, sequential conversion mode)...................................319 
 Software trigger mode (select mode, single conversion mode)..........................................320 
 Software trigger mode (scan mode, sequential conversion mode).....................................321 
 Software trigger mode (scan mode, single conversion mode)............................................322 
 Hardware trigger no-wait mode (select mode, sequential conversion mode).....................323 
 Hardware trigger no-wait mode (select mode, single conversion mode)............................324 
 Hardware trigger no-wait mode (scan mode, sequential conversion mode).......................325 
 Hardware trigger no-wait mode (scan mode, single conversion mode)..............................326 
 Hardware trigger wait mode (select mode, sequential conversion mode)..........................327 
 Hardware trigger wait mode (select mode, single conversion mode) .............................328 
 Hardware trigger wait mode (scan mode, sequential conversion mode)........................329 
 Hardware trigger wait mode (scan mode, single conversion mode) ...............................330 
 A/D converter setup flowchart.....................................................................................................331 
 Setting up software trigger mode.........................................................................................331 
 Setting up hardware trigger no-wait mode...........................................................................332 
 Setting up hardware trigger wait mode................................................................................333 
 Setup when temperature sensor output voltage/internal reference voltage is selected .....334 
 Setting up test mode............................................................................................................335 
 SIGMA-DELTA ADC....................................................................................336
 Overview .....................................................................................................................................336 
 Description of basic functions.....................................................................................................336 
 Description of ADC working principle .........................................................................................337 
 LDO......................................................................................................................................337 
 Analog inputs .......................................................................................................................337 
 Temperature sensor.............................................................................................................337 
 Low noise programmable gain amplifier..............................................................................337 
 ADC clock, output data rate.................................................................................................338 
 Reset and sleep mode.........................................................................................................339 
 Setup time............................................................................................................................339 
 SPI Serial Interface.....................................................................................................................340 
 Digital output codes .............................................................................................................340 

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 Data ready/data input and output (DRDYB/DOUT).............................................................340 
 Serial input clock (SCLK).....................................................................................................340 
 Serial data transmission.......................................................................................................341 
 Function configuration..........................................................................................................342 
 Description of SPI opcode command..................................................................................343 
 Cautions for SPI Communication.........................................................................................343 
 Related registers.........................................................................................................................344 
 Sigma-Delta ADC control register 1.....................................................................................344 
 Sigma-Delta ADC control register 2.....................................................................................345 
 Sigma-Delta ADC control register 3.....................................................................................346 
 Sigma-Delta ADC control register 4.....................................................................................347 
 D/A CONVERTER........................................................................................348 
 Function of D/A converter...........................................................................................................348 
 Structure of D/A converter ..........................................................................................................349 
 Registers for controlling D/A converter.......................................................................................350 
 Peripheral enable register 1 (PER1)....................................................................................350 
 D/A converter mode register (DAM) ....................................................................................351 
 D/A conversion value setting register i (DACSi) (i=0) .........................................................351 
 Event output destination select register n (ELSELRn), n= 00~15.......................................351 
 Operation of D/A Converter ........................................................................................................352 
 Operation in Normal Mode...................................................................................................352 
 Operation in real-time output mode.....................................................................................353 
 D/A conversion output timing...............................................................................................354 
 Cautions for D/A Converter.........................................................................................................355 
 COMPARATOR...........................................................................................356 
 Function of comparator...............................................................................................................356 
 Structure of comparator..............................................................................................................357 
 Registers for controlling comparator...........................................................................................359 
 Peripheral enable register 1 (PER1)....................................................................................360 
 Comparator mode setting register (COMPMDR) ................................................................361 
 Comparator filter control register (COMPFIR).....................................................................362 
 Comparator output control register (COMPOCR) ...............................................................364 
 Comparator negative reference selection register (CnREFS).............................................366 
 Comparator positive input selection register (CMPSELn)...................................................367 
 Comparator hysteresis control register (CMPnHY).............................................................368 
 Operation.....................................................................................................................................369 
 Digital filter of comparator n (n=0, 1) ...................................................................................371 
 Comparator n interrupt (n=0, 1)...........................................................................................371 
 Event signal output to the coordination controller (EVENTC).............................................372 