Cypress Semiconductor CY7C1034DV33 Bedienungsanleitung

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-08351 Rev. *C Revised January 16, 2009

CY7C1034DV33

6-Mbit (256K X 24) Static RAM

Features

■High speed

❐tAA = 10 ns

■Low active power

❐ICC = 175 mA at 10 ns

■Low CMOS standby power

❐ISB2 = 25 mA

■Operating voltages of 3.3 ± 0.3V

■2.0V data retention

■Automatic power down when deselected

■TTL compatible inputs and outputs

■Easy memory expansion with CE1, CE2, and CE3features

■Available in Pb-free standard 119-Ball PBGA

Functional Description

The CY7C1034DV33 is a high performance CMOS static RAM

organized as 256K words by 24 bits. This device has an

automatic power down feature that significantly reduces power

consumption when deselected.

To write to the device, enable the chip (CE1LOW, CE2HIGH,

and CE3LOW) while forcing the Write Enable (WE) input LOW.

To read from the device, enable the chip by taking CE1LOW, CE2

HIGH, and CE3LOW, while forcing the Output Enable (OE) LOW

and the Write Enable (WE) HIGH. See the Truth Table on page

7 for a complete description of Read and Write modes.

The 24 IO pins (IO0 to IO23) are placed in a high impedance state

when the device is deselected (CE1HIGH, CE2LOW, or CE3

HIGH) or when the output enable (OE) is HIGH during a write

operation. (CE1LOW, CE2HIGH, CE3LOW, and WE LOW).

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

256K x 24

ARRAY

– IO

, CE

CONTROL LOGIC

Logic Block Diagram

A(9:0)

A(17:10)

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CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 2 of 9

Selection Guide

Description –10 Unit

Maximum Access Time 10 ns

Maximum Operating Current 175 mA

Maximum CMOS Standby Current 25 mA

Pin Configuration

Figure 1. 119-Ball PBGA Top View [1]

1234567

ANCAAAAANC

BNC A A CE1AANC

CIO12 NC CE2ACE

3NC IO0

DIO13 VDD VSS VSS VSS VDD IO1

EIO14 VSS VDD VSS VDD VSS IO2

FIO15 VDD VSS VSS VSS VDD IO3

GIO16 VSS VDD VSS VDD VSS IO4

HIO17 VDD VSS VSS VSS VDD IO5

JNC VSS VDD VSS VDD VSS NC

KIO18 VDD VSS VSS VSS VDD IO6

LIO19 VSS VDD VSS VDD VSS IO7

MIO20 VDD VSS VSS VSS VDD IO8

NIO21 VSS VDD VSS VDD VSS IO9

PIO22 VDD VSS VSS VSS VDD IO10

RIO23 NC NC NC NC NC IO11

TNC A A WE AANC

UNC A A OE AANC

Note

1. NC pins are not connected on the die.

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CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 3 of 9

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage on VCC Relative to GND [2]....–0.5V to +4.6V

DC Voltage Applied to Outputs

in High Z State [2]................................... –0.5V to VCC + 0.5V

DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage............. ...............................>2001V

(MIL-STD-883, Method 3015)

Latch up Current...................................................... >200 mA

Operating Range

Range Ambient

Temperature VCC

Industrial –40°C to +85°C3.3V±0.3V

DC Electrical Characteristics

Over the operating range

Parameter Description Test Conditions [3] –10 Unit

Min Max

VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3 V

VIL [2] Input LOW Voltage –0.3 0.8 V

IIX Input Leakage Current GND < VI< VCC –1 +1 μA

IOZ Output Leakage Current GND < VOUT <VCC, output disabled –1 +1 μA

ICC VCC Operating Supply

Current

VCC = Max, f = fMAX = 1/tRC,

IOUT = 0 mA CMOS levels

175 mA

ISB1 Automatic CE Power Down

Current — TTL Inputs

Max VCC, CE1, CE3> VIH, CE2 <VIL,

VIN > VIH or VIN < VIL, f = fMAX

30 mA

ISB2 Automatic CE Power Down

Current — CMOS Inputs

Max VCC, CE1, CE3> VCC – 0.3V, CE2 <0.3V,

VIN > VCC – 0.3V, or VIN < 0.3V, f = 0

25 mA

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = 3.3V 8 pF

COUT IO Capacitance 10 pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions 119-Ball

PBGA Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still air, soldered on a 3 × 4.5 inch,

four layer printed circuit board

20.31 °C/W

ΘJC Thermal Resistance

(Junction to Case)

8.35 °C/W

Notes

2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.

3. CE refers to a combination of CE1, CE2, and CE3. CE is active LOW when CE1 is LOW, CE2is HIGH, and CE3 is LOW. CE is HIGH when CE1 is HIGH or CE2is LOW

or CE3 is HIGH.

[+] Feedback

CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 4 of 9

Figure 2. AC Test Loads and Waveform [4]

AC Switching Characteristics

Over the operating range [5]

Parameter Description –10 Unit

Min Max

Read Cycle

tpower [6] VCC(Typical) to the First Access 100 μs

tRC Read Cycle Time 10 ns

tAA Address to Data Valid 10 ns

tOHA Data Hold from Address Change 3 ns

tACE CE Active LOW to Data Valid [3] 10 ns

tDOE OE LOW to Data Valid 5 ns

tLZOE OE LOW to Low Z [7] 1ns

tHZOE OE HIGH to High Z [7] 5ns

tLZCE CE Active LOW to Low Z [3, 7] 3ns

tHZCE CE Deselect HIGH to High Z [3, 7] 5ns

tPU CE Active LOW to Power Up [3, 8] 0ns

tPD CE Deselect HIGH to Power Down [3, 8] 10 ns

90%

10%

3.0V

GND

90%

10%

All input pulses

3.3V

OUTPUT

5 pF*

(a)

(b)

R1 317 Ω

351Ω

Fall Time:> 1V/ns

(c)

OUTPUT

50Ω

Z0= 50Ω

VTH = 1.5V

30 pF*

*Capacitive Load consists of all

components of the test environment

Rise Time > 1V/ns

*Including jig

and scope

Notes

4. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0V). 100 μs (tpower) after reaching the minimum operating VDD,

normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use

output loading as shown in part a) of the AC Test Loads and Waveform [4], unless specified otherwise.

6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.

7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady

state voltage.

8. These parameters are guaranteed by design and are not tested.

[+] Feedback

CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 5 of 9

Write Cycle [9, 10]

tWC Write Cycle Time 10 ns

tSCE CE Active LOW to Write End [3] 7ns

tAW Address Setup to Write End 7 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 7 ns

tSD Data Setup to Write End 5.5 ns

tHD Data Hold from Write End 0 ns

tLZWE WE HIGH to Low Z [7] 3ns

tHZWE WE LOW to High Z [7] 5ns

Data Retention Characteristics

Over the operating range

Parameter Description Conditions [3] Min Typ Max Unit

VDR VCC for Data Retention 2 V

ICCDR Data Retention Current9 VCC = 2V, CE1, CE3> VCC – 0.2V,

CE2 <0.2V, VIN > VCC – 0.2V or VIN < 0.2V

25 mA

tCDR [11] Chip Deselect to Data Retention Time 0 ns

tR [12] Operation Recovery Time tRC ns

Figure 3. Data Retention Waveform

AC Switching Characteristics (continued)

Over the operating range [5]

Parameter Description –10 Unit

Min Max

3.0V3.0V

tCDR

VDR > 2V

DATA RETENTION MODE

VCC

Notes

9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2HIGH, CE3LOW, and WE LOW. Chip enables must be active and WE must be LOW

to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal

that terminates the write.

10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

11. Tested initially and after any design or process changes that may affect these parameters.

12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs.

[+] Feedback

CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 6 of 9

Switching Waveforms

Figure 4. Read Cycle No. 1 (Address Transition Controlled) [13, 14]

Figure 5. Read Cycle No. 2 (OE Controlled) [3, 14, 15]

Figure 6. Write Cycle No. 1 (CE Controlled) [3, 16, 17]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

HIGH

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

DATA IO

ADDRESS

Notes

13. Device is continuously selected. OE, CE = VIL.

14. WE is HIGH for read cycle.

15. Address valid before or similar to CE transition LOW.

16. Data IO is high impedance if OE = VIH.

17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

[+] Feedback

CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 7 of 9

Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]

Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]

Truth Table

CE1CE2CE3OE WE IO0 – IO23 Mode Power

HXXXXHighZ PowerDown Standby(I

SB)

X L X X X High Z Power Down Standby (ISB)

X X H X X High Z Power Down Standby (ISB)

L H L L H Full Data Out Read Active (ICC)

L H L X L Full Data In Write Active (ICC)

L H L H H High Z Selected, Outputs Disabled Active (ICC)

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

NOTE 18

ADDRESS

DATA IO

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

NOTE 18

ADDRESS

DATA IO

Note

18. During this period, the IOs are in the output state and input signals are not applied.

[+] Feedback

CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 8 of 9

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

10 CY7C1034DV33-10BGXI 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial

Package Diagram

Figure 9. 119-Ball PBGA (14 x 22 x 2.4 mm)

51-85115-*B

[+] Feedback

CY7C1034DV33

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used

for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use

as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support

systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-08351 Rev. *C Revised January 16, 2009 Page 9 of 9

All product and company names mentioned in this document are the trademarks of their respective holders.

Document History Page

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Document Title: CY7C1034DV33 6-Mbit (256K X 24) Static RAM

Document Number: 001-08351

REV. ECN NO. Orig. of

Change

Submission

Date Description of Change

** 469517 NXR See ECN New data sheet

*A 499604 NXR See ECN Added note 1 for NC pins

Changed ICC specification from 150 mA to 185 mA

Updated Test Condition for ICC in DC Electrical Characteristics table

Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics

Table on page 4

*B 1462586 VKN/SFV See ECN Converted from preliminary to final

Updated block diagram

Changed ICC specification from 185 mA to 225 mA

Updated thermal specs

*C 2644842 VKN/PYRS 01/23/09 Replaced Commercial range with the Industrial

Replaced 8 ns speed with 10 ns

[+] Feedback

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