Cypress Semiconductor CY7C1399B Bedienungsanleitung

32K x 8 3.3V Static RAM

CY7C1399B

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-05071 Rev. *A Revised June 19, 2001

399B

Features

• Single 3.3V power supply

• Ideal for low-voltage cache memory applications

• High speed

—10/12/15 ns

• Low active power

—216 mW (max.)

• Low-power alpha immune 6T cell

• Plastic SOJ and TSOP packaging

Functional Description

The CY7C1399B is a high-performance 3.3V CMOS Static

RAM organized as 32,768 words by 8 bits. Easy memory ex-

pansion is provided by an active LOW Chip Enable (CE) and

active LOW Output Enable (OE) and three-state drivers. The

device has an automatic power-down feature, reducing the

power consumption by more than 95% when deselected.

An active LOW Write Enable signal (WE) controls the writing/

readingoperationof the memory. When CE and WE inputsare

both LOW, data on the eight data input/output pins (I/O0

through I/O7) is written into the memory location addressed by

the address present on the address pins (A0through A14).

Reading the device is accomplished by selecting the device

and enabling the outputs, CE and OE active LOW, while WE

remains inactive or HIGH. Under these conditions, the con-

tents of the location addressed by the information on address

pins is present on the eight data input/output pins.

The input/output pins remain in a high-impedance stateunless

the chip is selected, outputs are enabled, and Write Enable

(WE) is HIGH. The CY7C1399B is availablein 28-pin standard

300-mil-wide SOJ and TSOP Type I packages.

Logic Block Diagram Pin Configurations

14 15

Top View

SOJ

GND

A10

A11

A12

A13

VCC

I/O7

I/O6

I/O5

I/O4

A14

I/O0

I/O1

I/O2

I/O3

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

POWER

DOWN

I/O0

I/O1

I/O2

I/O3

32K x 8

ARRAY

I/O7

I/O6

I/O5

I/O4

Selection Guide

1399B-10 1399B-12 1399B-15 1399B-20

Maximum Access Time (ns) 10 12 15 20

Maximum Operating Current (mA) 60 55 50 45

Maximum CMOS Standby Current (µA) 500 500 500 500

L50 50 50 50

CY7C1399B

Document #: 38-05071 Rev. *A Page 2 of 10

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V

DC Voltage Applied to Outputs

in High Z State[1]....................................–0.5V to VCC + 0.5V

DC Input Voltage[1] ................................–0.5V to VCC + 0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Pin Configuration

510

Top View

TSOP

VCC

I/O7

I/O6

I/O5

GND

I/O2

I/O1

I/O4

I/O0

A14

A10

A11 A13

A12

I/O3

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 3.3V ±300 mV

Industrial –40°C to +85°C 3.3V ±300 mV

Electrical Characteristics Over the Operating Range[1]

7C1399B-10 7C1399B-12

Parameter Description Test Conditions Min. Max. Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC

+0.3V 2.2 VCC

+0.3V V

VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V

IIX Input Load Current –1+1–1+1 µA

IOZ Output Leakage

Current GND ≤VI≤VCC,

OutputDisabled –5+5–5+5 µA

IOS Output Short

Circuit Current[2] VCC = Max., VOUT = GND –300 –300 mA

ICC VCC Operating

Supply Current VCC = Max., IOUT = 0 mA,

f = fMAX = 1/tRC 60 55 mA

ISB1 Automatic CE Power-Down

Current —TTL Inputs Max. VCC, CE ≥VIH,

VIN ≥VIH, or VIN ≤VIL,f = fMAX 5 5 mA

L44mA

ISB2 Automatic CE Power-Down

Current —CMOS Inputs[3] Max.VCC,CE≥VCC–0.3V,VIN≥VCC

–0.3V, or VIN ≤0.3V,

WE≥VCC–0.3VorWE≤0.3V,f = fMAX

500 500 µA

L5050 µA

Notes:

1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

3. Device draws low standby current regardless of switching on the addresses.

CY7C1399B

Document #: 38-05071 Rev. *A Page 3 of 10

Electrical Characteristics Over the Operating Range (continued)

1399B-15 1399B-20

Parameter Description Test Conditions Min. Max. Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC

+0.3V 2.2 VCC

+0.3V V

VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V

IIX Input Load Current –1+1 –1+1 µA

IOZ Output Leakage Current GND ≤VI≤VCC,

Output Disabled –5+5 –5+5 µA

IOS Output Short Circuit

Current[2] VCC = Max., VOUT = GND –300 –300 mA

ICC VCC Operating

Supply Current VCC = Max., IOUT = 0 mA,

f = fMAX = 1/tRC 50 45 mA

ISB1 AutomaticCEPower-Down

Current —TTL Inputs Max. VCC, CE ≥VIH,

VIN ≥VIH, or VIN ≤VIL,

f = fMAX

5 5 mA

L 4 4 mA

ISB2 AutomaticCEPower-Down

Current —CMOS Inputs[3] Max. VCC,CE ≥VCC–0.3V,VIN ≥

VCC –0.3V, or VIN ≤0.3V,

WE≥VCC–0.3V or WE≤0.3V,

f=fMAX

500 500 µA

L50 50 µA

Capacitance[4]

Parameter Description Test Conditions Max. Unit

CIN: Addresses Input Capacitance TA= 25°C, f = 1 MHz, VCC = 3.3V 5pF

CIN: Controls 6pF

COUT Output Capacitance 6pF

AC Test Loads and Waveforms

Note:

4. Tested initially and after any design or process changes that may affect these parameters.

3.0V

3.3V

OUTPUT

R1 317Ω

351Ω

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

≤3ns ≤3ns

OUTPUT 1.73V

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

167Ω

CY7C1399B

Document #: 38-05071 Rev. *A Page 4 of 10

Switching Characteristics Over the Operating Range[5]

1399B–10 1399B–12

Parameter Description Min. Max. Min. Max. Unit

READ CYCLE

tRC Read Cycle Time 10 12 ns

tAA Address to Data Valid 10 12 ns

tOHA Data Hold from Address Change 3 3 ns

tACE CE LOW to Data Valid 10 12 ns

tDOE OE LOW to Data Valid 5 5 ns

tLZOE OE LOW to Low Z[6] 00ns

tHZOE OE HIGH to High Z[6, 7] 55ns

tLZCE CE LOW to Low Z[6] 33ns

tHZCE CE HIGH to High Z[6, 7] 56ns

tPU CE LOW to Power-Up 0 0 ns

tPD CE HIGH to Power-Down 10 12 ns

WRITE CYCLE[8, 9]

tWC Write Cycle Time 10 12 ns

tSCE CE LOW to Write End 8 8 ns

tAW Address Set-Up to Write End 7 8 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Set-Up to Write Start 0 0 ns

tPWE WE Pulse Width 7 8 ns

tSD Data Set-Up to Write End 5 7 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High Z[8] 77ns

tLZWE WE HIGH to Low Z[6] 33ns

Notes:

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOL/IOH and capacitance CL= 30 pF.

6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less thantLZWE for any given device.

7. tHZOE, tHZCE, tHZWE are specified with CL= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.

8. The internal write time of the memory is defined by the overlap of CELOW and WE LOW. Both signalsmust be LOWto initiatea write and eithersignal can terminate

a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

9. The minimum write cycle time for write cycle #3 (WEcontrolled, OE LOW) is the sum of tHZWE and tSD.

CY7C1399B

Document #: 38-05071 Rev. *A Page 5 of 10

Switching Characteristics Over the Operating Range[5] (Continued)

1399B–15 1399B–20

Parameter Description Min. Max. Min. Max. Unit

READ CYCLE

tRC Read Cycle Time 15 20 ns

tAA Address to Data Valid 15 20 ns

tOHA Data Hold from Address Change 3 3 ns

tACE CE LOW to Data Valid 15 20 ns

tDOE OE LOW to Data Valid 6 7 ns

tLZOE OE LOW to Low Z[6] 0 0 ns

tHZOE OE HIGH to High Z[6, 7] 6 6 ns

tLZCE CE LOW to Low Z[6] 3 3 ns

tHZCE CE HIGH to High Z[6, 7] 7 7 ns

tPU CE LOW to Power-Up 0 0 ns

tPD CE HIGH to Power-Down 15 20 ns

WRITE CYCLE[8, 9]

tWC Write Cycle Time 15 20 ns

tSCE CE LOW to Write End 10 12 ns

tAW Address Set-Up to Write End 10 12 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Set-Up to Write Start 0 0 ns

tPWE WE Pulse Width 10 12 ns

tSD Data Set-Up to Write End 810 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High Z[8] 7 7 ns

tLZWE WE HIGH to Low Z[6] 3 3 ns

Data Retention Characteristics (Over the Operating Range - L version only)

Parameter Description Conditions Min. Max. Unit

VDR VCC for Data Retention 2.0 V

ICCDR Data Retention Current Com’l VCC = VDR = 2.0V,

CE > VCC –0.3V,

VIN > VCC –0.3V or

VIN < 0.3V

020 uA

tCDR Chip Deselect to Data

Retention Time 0ns

tROperation Recovery Time tRC ns

CY7C1399B

Document #: 38-05071 Rev. *A Page 6 of 10

Data Retention Waveform

3.0V3.0V

tCDR

VDR >2V

DATA RETENTION MODE

VCC

Switching Waveforms

Notes:

10. Device is continuously selected. OE, CE = VIL.

11. WE is HIGH for read cycle.

12. Address valid prior to or coincident with CEtransition LOW.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

Read Cycle No. 1[10, 11]

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

DATA OUT HIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOE

tHZCE

tPD

HIGH

VCC

SUPPLY

CURRENT

Read Cycle No. 2[11, 12]

CY7C1399B

Document #: 38-05071 Rev. *A Page 7 of 10

Notes:

13. Data I/O is high impedance if OE= VIH.

14. If CE goes HIGH simultaneously with WE HIGH,the output remains in a high-impedance state.

15. During this period, the I/Os are in the output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAINVALID

Write Cycle No. 1 (WE Controlled)[8, 13, 14]

NOTE 15

tWC

tAW

tSA tHA

tHD

tSD

tSCE

DATA I/O

ADDRESS

DATAINVALID

Write Cycle No. 2 (CE Controlled)[8, 13, 14]

DATA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATAIN VALID

Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14]

NOTE 15

CY7C1399B

Document #: 38-05071 Rev. *A Page 8 of 10

Truth Table

CE WE OE Input/Output Mode Power

H X X High Z Deselect/Power-Down Standby (ISB)

L H L Data Out Read Active (ICC)

L L X Data In Write Active (ICC)

L H H High Z Deselect, Output Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

10 CY7C1399B-10VC V21 28-Lead Molded SOJ Commercial

CY7C1399B-10ZC Z28 28-Lead Thin Small Outline Package

CY7C1399BL-10VC V21 28-Lead Molded SOJ

CY7C1399BL-10ZC Z28 28-Lead Thin Small Outline Package

12 CY7C1399B–12VC V21 28-Lead Molded SOJ

CY7C1399B–12ZC Z28 28-Lead Thin Small Outline Package

CY7C1399BL-12VC V21 28-Lead Molded SOJ

CY7C1399BL-12ZC Z28 28-Lead Thin Small Outline Package

CY7C1399B–12VI V21 28-Lead Molded SOJ Industrial

CY7C1399B–12ZI Z28 28-Lead Thin Small Outline Package

15 CY7C1399B–15VC V21 28-Lead Molded SOJ Commercial

CY7C1399B–15ZC Z28 28-Lead Thin Small Outline Package

CY7C1399BL-15VC V21 28-Lead Molded SOJ

CY7C1399BL-15ZC Z28 28-Lead Thin Small Outline Package

CY7C1399B–15VI V21 28-Lead Molded SOJ Industrial

CY7C1399B–15ZI Z28 28-Lead Thin Small Outline Package

20 CY7C1399B–20VC V21 28-Lead Molded SOJ Commercial

CY7C1399B–20ZC Z28 28-Lead Thin Small Outline Package

CY7C1399BL-20VC V21 28-Lead Molded SOJ

CY7C1399BL-20ZC Z28 28-Lead Thin Small Outline Package

CY7C1399B–20VI V21 28-Lead Molded SOJ Industrial

CY7C1399B–20ZI Z28 28-Lead Thin Small Outline Package

CY7C1399B

Document #: 38-05071 Rev. *A Page 9 of 10

of any circuitry other than circuitryembodied in a Cypress Semiconductorproduct. Nor does it convey orimply any license under patent orother rights. CypressSemiconductor doesnot authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

28-Lead (300-Mil) Molded SOJ V21

51-85031-B

28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28

51-85071-*G

CY7C1399B

Document #: 38-05071 Rev. *A Page10 of10

Revision History

Document Title: CY7C1399B 32K x 8 3.3V Static RAM

Document Number: 38-05071

REV. ECN NO. ISSUE DATE ORIG. OF

CHANGE DESCRIPTION OF CHANGE

** 107264 05/25/01 SZV Change from Spec #: 38-01102 to 38-05071

*A 107533 06/28/01 MAX Add Low Power

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