Digital Equipment BM873 Bedienungsanleitung

BM873

restart/loader

DEC-II-H873A-B-D

digital equipment. corporation · maynard,massachusetts

Digital Equipment Corporation

The material

this manual

for informational

purposes and

subject to change without notice.

Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this

manual.

Printed in U.S.A.

The following are trademarks

Digital Equipment

Corporation, Maynard, Massachusetts:

DEC

FLIP CHIP

DIGITAL

UNIBUS

PDP

FOCAL

COMPUTER

LAB

First Edition, January 1974

2nd Printing (Rev), April 1974

CHAPTER 1

1.1

1.2

1.3

CHAPTER 2

2.l

2.l.1

2.1.2

2.1.3

2.2

CHAPTER 3

3.l

3.2

CHAPTER 4

4.1

CHAPTERS

CHAPTER 6

Figure No.

1·1

1·2

2·1

4·1

Table

No.

1-1

2-1

DESCRIPTION

INTRODUCTION

......

GENERAL

DESCRIPTION

FUNCTIONAL DESCRIPTION

CONTENTS

INST

ALLATION AND CHECKOUT

INSTALLATION

Start Address Selection

Jumper

Selection

...

CPU Addressing

with

Volatile Memory

CHECKOUT

...............

PROGRAMMING

POWER

FAIL

PROGRAMMING

OPTIONS

Page

1-1

1-2

2-1

2-3

3-1

USER

CUSTOM PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

INTERFACE

ENGINEER1NG DRAWINGS

ILLUSTRATIONS

Title

Remote

Start

Timing

......

Memory Read Timing

.....

External Interface Circuit Diode Matrix

Sample ROM Program

Data

Sheet

TABLES

Tide

BM873 Specifications

.....

BM873-YA

Option

Starting Addresses

iii

Page

1-3

2-2

4-2

Page

1-2

2-2

1.1

INTRODUCTION

CHAPTER

DESCRIPTION

This manual describes the operation and theory

the BM873 Restart/Loader. This option

intended for use with

the PDP-II family

processors. The BM873

• serves

general purpose loader for processors

the

family,

• contains bootstran loaders for

alI

common devices,

• provides the capability

ofloading

with a "hidden console",

• permits starting from several sources e.g., pushbutton, Watchdog Timer,

MODEM

control, power fail,

etc.,

•

gives

PDP-II systems an initial program load capability,

• contains at least four starting addresses, and

• permits the calling

a special user

ROM

program.

assumed

that

the reader is thoroughly familiar with the operation

ofthe

PDP-ll

processor with which this

option

used.

1.2 GENERAL DESCRIPTION

The BM873 option

mounted on a single quad-sized module which plugs into a small peripheral controller (SPC)

slot. In its basic version, it contains several bootstrap loader programs within a 128-word Read-Only Memory

(ROM). These programs may be loaded either from the console (Load Address and Start),

a JMP instruction in

the program,

external contact closure or voltage level. The external interface is made via an 8-pin

Mate-N-Lok connector. Specifications are listed in Table

I-I.

I-I

Table

1-1

BM873 Specifications

Capacity

Word length

ROM

cycle time

Voltage requirements

Current requirements

Operating temperature

Humidity

1.3

FUNCTIONAL

DESCRIPTION

128 words, read-only

(256 words optional)

bits

500

±5%

-15

±5%

1.0 A max @

2.0 rnA max @

-15

20%

to 95%

The BM873 consists

two basic sections: the Restart Sequencer and the

ROM.

Figure

1-1

shows the remote start timing. The Restart Sequencer takes contact closures or voltage levels and, after

filtering and delaying, sets one

four Start Address Select flip-flops. The setting

one

the flip-flops causes the

Begin

Load Sequence flip-flop

set; this, in turn, initiates two one-shots'

create a

BUS

LO/BUS

sequence. The processor responds

the sequence by performing its normal power-down and power-up trap

routines. Prior

the power-up sequence, however, the BM873 option asserts 773000 on the Unibus Address Lines.

a result, when the Program Counter (PC) and Processor Status Word

(PSW)

are restored, the data

taken from

locations 773024/26 (nonvolatile memory systems) or fpJm locations 773224/26 (volatile memory systems). Both

these addresses

are

locations within the BM873 option. The data from 773*24

173000; the data from 773*26

340, establishing a priority level

The data read from 773*24 (173000) will have an offset address ORed onto Offset Address bits 8 through

giving

a range

173000 to 173776. The offset address bits are enabled

one

the four Start Address Select flip-flops

via

a diode matrix (paragraph 2.1.1). Each bootstrap loader program has its own starting address, and it

this

address that

selected via the offset address bits.

The following sequence

operations would be typical:

• Close external switch and wait for switch filter delay.

• Assert

LO;

wait 6 ms.

• Assert

for 6 ms; then wait 8 ms.

• Drop

and assert address 773000.

• Wait for

INIT

finish.

• The processor enters power-up routine.

1-2

SWITCH

,/___

,,,,u,

"V\\._

---------------I111,-~

.........

,:........

-',,-

~-----------~\~~----_T:----~I

REC

_...;..;.1::.;5m~s:..........J

________

CLR

DLY

----..,

~-------~\~\-----------

20m.

START

ADR

S:::E::

___________

~~I~".:...S

-------1\

BEGIN LOAD

SEQ

--------....1-

-------~

\----1--------

BUS

ACLO L

---------.

\\-...J..i_--,I

BUS

DCLO L

------------:1

BUS

INIT

---------+__,

ASSERT ADR

773000

-------------1

CPUDLY

__________________________

-J

FETCH

3024/26

----+I

PWRUPTRAP-------------------

_____

--J

CPU-BEGIN EXECUTION

_______________________

.....J

ROM

PROGRAM

11-2408

Figure I-I Remote Start Timing

• The

BM873

option recognizes the fetch

address 773024 or 773224 and asserts 173XXX plus the 8-bit

offset address to the data lines.

• The processor reads location 773026 or 773226 which

always 000340 (priority

level

7).

• The processor

fetches.

the next instruction from the

ROM

in address range 773000-773776. From this

point, the bootstrap loader program contained in the

ROM

has control. (In the

PDP-ll/35

and

PDP-I 1/40 systems, the

PSW

fetched before the PC.)

actual power

fail

occurs in a nonvolatile memory system, the

BM873

option does nothing, and the power-down

and power-up traps work in the normal manner. If

actual power

fail

occurs in a volatile memory system, the

power-up jumpers in the processor

are

set for 173224. During power-up the processor

will

fetch from 173224; the

combination

address 773224 and no external lines asserted will cause the

BM873

option to assert line I

default case. Thus, in this case, the offset address selected for line 1becomes the bootstrap loader call for power fail.

Data

read from the

ROM

in two bytes. Address bits 7 through 1 are present at

all

times

via

the bus receivers.

Address bit 0

generated on the module.

is always clear prior to a read cycle. The setting

clocks the first

byte into a holding register and simultaneously changes the address to gate the second byte to the output drivers.

After a delay

about 200

ns,

the output gates are enabled and the

ROM

data

placed on the Unibus.

SSYN

asserted about 150

later, completing the read cycle. Figure

1-2

illustrates memory read timing.

1-3

ADR

8 CONTROL J

MSYN (READ)

AID

(1) H

----'

DLY

(0)

----,1'.

DATA

BUS

(I) H

------1

BUS SSYNL

-------.

500

LESS

200ns

l.DEPENDENT

BUS

LENGTH

11-

2407

Figure

1-2

Memory Read Timing

1-4

2.1

INSTALLATlON

CHAPTER

INSTALLATION

AND

CHECKOUT

Normally the

BM873

Restart/Loader

installed at the factory and no further installation

required. However,

this option

added

existing system,

may be necessary to add wiring to make the

and

signals

available. These signals are provided on the PDP-II/OS and PDP-ll/4S processors, and on the

DDll-B.

On the

PDP-ll/lS,

PDP-ll/20,

PDP-ll/3S, PDP-ll/40, and the DDII-A it

necessary to ensure that the

SPC

slot

containing the

BM873

has

BUS

and

BUS

wiring available

follows:

Pin CVl to B01Fl or B04Fl

(BUS

LO)

Pin CNI to

BOI

F2 or B04F2

(BUS

LO)

If the wiring

not present,

must be added by hand-wiring, using a

wire

color different from that

the existing

backplane wiring.

NOTE

The

BM873

option must be on the

CPU

side

any bus buffer.

2.1.1 Start Address Selection

Each

the four external interface circuits has an associated address which must

specified for that circuit to be

addressed. Each address consists

a fixed high-order portion (773XXX) and a low-order portion (bits 8 through 1)

that

selected by adding or cutting diodes (Figure 2-1).

When

adding diodes, a low.wattage iron should be used and

care should

taken with the plated mounting holes,

that the plating

not lifted from the laminate by the heat.

The

diodes

(DEC

type 664 or IN3606) should be positioned

that their cathodes point toward the gold fingers

the module.

Table

2-1

lists starting addresses for various devices used with the BM873-YA Restart/Loader. The three rightmost

digits

the address represent the low-order portion

be selected

via

diodes.

The diagnostic program for this option contains a listing

the loader program in the comments portion

the Data

Compare section. That diagnostic will be updated to contain the starting addresses and listing

future variations

(·YB, etc.).

2-1

BIT

LINE

1 -

~1~1~1~1~1~1~loll4-----,

LINE 2 -

~i~l~t~t~t~t~t~t

1-------1

LINE

~t~t~t~t~t~t~t~1

LINE

~1~1~1~I~r~I~I~r

BM873

MODULE

Address

773000

773010

773020

773030

773050

773

100

773 144

773210

773230

773312

Figure 2·1 External Interface Circuit Diode Matrix

Table

2-1

BM873-YA

Option

Starting Addresses

Device Type

RFII

RKII

Transfer

Address contained in Switch Register

TCII

TMl1

RPll

RCl1

KL11 /DL11 -Console

TTY

Reader

TAll

PCII--Paper

Tape Reader

2-2

11-2406

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