CIRCUIT DESCRIPTION
Refer to the Schematic Diagram and the Bloc Diagram while you read the following description.
To help you locate parts in the Keyer or on the Schematic, the resistors, capacitors and other com-
ponents are numbered in the following groups:
1 – 99 Parts mounted on the circuit board.
101 – 100 Parts mounted on the chassis.
The following terms and their definitions will be used during this description:
Mar : Key-down condition; IC3 pin 12 is high
Space: Key-up condition; IC3 pin 12 is low
Dot bit: Dot-mar and space following
Dash bit: Dash-mar and Space following
When you operate the paddles, the "present bit memory" commands the cloc enable circuit to
Start a bit and insures that the present bit is completed before another Starts. The "next bit mem-
ories" retain the information of which bit is next (a dot or dash), if a dot or dash was eyed before
the present bit is completed. After the present bit is completed, the "resets" load the "present bit
memory" with the information that is in the "next bit memories." Each dot, dash, and off time is
uniform because of the cloc which produces uniformly spaced pulses. The bit generator then re-
sponds to the cloc pulses and the dot/dash determining line to produce a dot (or a dash that is
three times longer than the dot) and an off time. The Output circuitry drives the eyer Output and
sidetone circuitry.
Because of the sequence of digital logic involved, the cloc will be explained first.
CLOCK
The cloc consists of transistors Q1, Q2, and their associated circuitry. When IC1 pin 8 is high the
cloc is disabled. Capacitor C3 charges through diode 01 and biases Q1 off. With Q1 off, the base
of Q2 is high. Therefore, Q2 is also off and the cloc output is low. Note that the high on IC1 pin 8
is also applied through D2 to IC4 pin 5. When IC1 pin 8 goes low (bit being sent), IC4A changes
state. D1 is then bac -biased and C3 begins to discharge through resistor R9, Speed control R101,
and resistor R11. When its voltage drops to the base Potential of Q1, Q1 begins to turn on, The
collector of Q1 and the base of Q2 begin to go less positive and turn on Q2. As Q2 turns on, its ris-
ing collector potential is coupled through capacitor C4 to the base of Ql and turns it on harder.
Thus the condition is regenerative and happens very quic ly.
The output is now high. This high on the collector of Q2 is applied to IC4 pin 5 by diode D3. C3
charges quic ly through resistor R7, the base-emitter junction of Q2 and Q1. C4 discharges and Q1
turns off, thus turning off Q2. This high-to-low transition on IC4 pin 5 again changes the state of
IC4A. Note that D2, D3 and resistor R12 form an "OR" gate and that IC4A changes state when IC1
pin 8 goes low (when the paddle is first eyed) and on the trailing edge of each cloc pulse.
BIT GENERATOR
The bit generator is composed of IC4A and B and IC3C. In the resting condition, IC4A and B are
reset (Q Outputs low). The highs on IC3 pins 1, 2, and 13 cause IC3 pin 12 to be low ( ey-up). If
IC4 pin 2 is low, IC4B cannot change state. The waveform in Figure 10 show how dots and dashes
are formed. Note that if IC4 pin 2 is low, dots are generated; if it is high, dashes are generated.
