Intersil ISL28208SOICEVAL2Z Bedienungsanleitung

Application Note 1658

ISL28208SOICEVAL2Z Evaluation Board User’s Guide

Introduction

The ISL28208SOICEVAL2Z evaluation board is designed to

evaluate the performance of the ISL28208 dual Operational

Amplifier. The ISL28208 is a dual low power precision

amplifier that features a common mode input voltage range

extending to 0.5V below the V- rail, a rail-to-rail differential

input voltage range for use as a comparator, and rail-to-rail

output voltage swing, which makes it ideal for single supply

applications where input operation at ground is important.

With a wide operating range from 3V to 40V, in combination

with its precision, low power, and small footprint, ISL28208

provides the user with outstanding value and flexibility relative

to similar competitive parts.

Reference Documents

• ISL28208 Data Sheet, FN6935

Evaluation Board Key Features

• Single Supply Operation: +9V to +40V

• Dual Supply Operation: ±4.5V to ±20V

• Singled-Ended or Differential Input Operation

• External VREF input

• Banana Jack Connectors for Power Supply and VREF Inputs

• BNC Connectors for Op Amp Input and Output Terminals

• Convenient PCB Pads for Op Amp Input/Output Impedance

Power Supplies (Figure 1)

External power connections are made through the V+, V-, VREF,

and GND connections on the evaluation board. The circuit can

operate from a single supply or from dual supplies. For single

supply operation, the V- and GND pins are tied together to the

negative or ground reference of the power supply. For split

supplies, V+ and V- terminals connect to their respective

supply terminals. De-coupling capacitors C2 and C4 provide

low-frequency power-supply filtering, while additional

capacitors, C3 and C5, which are connected close to the part,

filter out high frequency noise. Anti-reverse diode D1 (optional)

protects the circuit in the momentary case of accidentally

reversing the power supplies to the evaluation board. The VREF

pin can be connected to ground to establish a ground

referenced input for split supply operation, or can be externally

set to any reference level for single supply operation.

FIGURE 1. POWER SUPPLY CIRCUIT

CLOSE TO DUT

0.01µF

1R31

R16

C2 C4

C3 C5

J11

J14

J12

J13

1µF 1µF

VREF

V+

V-

FIGURE 2. PRECISION AMPLIFIER WITH G = -10V/V

INA-

INA+

R13/R23

ISL28208

+4.5V

V-

V+

10kΩ

100kΩ

VREF

100kΩ

VOUT

GAIN = -10V/V

TO +20V

PRECISION

SENSOR

-4.5V TO -20V

R11/R24

R14/R21

R18/R19

INB-

INB+

1/7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

July 26, 2011

AN1658.0

Application Note 1658

2AN1658.0

July 26, 2011

Amplifier Configuration (Figure 3)

The schematic of the op amp input stage with the components

supplied is shown in Figure 3, with a closed loop gain of 10V/V.

The differential amplifier gain is expressed in Equation 1:

For single-ended input with an inverting gain G = -10V/V, the IN+

input is grounded and the signal is supplied to the IN- input. VREF

can be connected to a reference voltage between the V+ and V-

supply rails. For non-inverting operation with G = 11V/V, the IN-

input is grounded and the signal is supplied to the IN+ input. The

non-inverting gain is strongly dependent on any resistance from

IN- to GND. For good gain accuracy, a 0Ωresistor should be

installed on the empty R5 pad.

User-selectable Options

(Figures 3 and 4)

Component pads are included to enable a variety of

user-selectable circuits to be added to the amplifier inputs, the

VREF input, outputs and the amplifier feedback loops.

A voltage divider (Figure 3, R18 and R15) can be added to

establish a power supply-tracking common mode reference

using the VREF input. The inverting and non-inverting inputs have

additional resistor placements for adding input attenuation, or to

establish input DC offsets through the VREF pin.

The output (Figure 4) also has additional resistor and capacitor

placements for filtering and loading.

NOTE: Operational amplifiers are sensitive to output capacitance

and may oscillate. In the event of oscillation, reduce output

capacitance by using shorter cables, or add a resistor in series

with the output.

VOUT VIN+

(VIN-)RF

(• RIN)⁄–VREF

+= (EQ. 1)

DNP

J1 R1

R14

R18R15

R13R11

10k

DNP

10k

DNP

100k

OPEN

100k

VREF

TO INA -

TO INA +

FROM VOUTA

IN+A

IN-A

FIGURE 3. INPUT STAGE

OUT A

R26 J15

R28

DNP

OPEN

VOUT_A

FIGURE 4. OUTPUT STAGE

TABLE 1. ISL28208SOICEVAL2Z COMPONENTS PARTS LIST

DEVICE # DESCRIPTION COMMENTS

C2, C4 CAP, SMD, 1206, 1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling

C3, C5 CAP, SMD, 0603, 0.01µF, 50V, 10%, X7R, ROHS Power Supply Decoupling

C1, C6, C7, C8, C9, C10 CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable capacitors - not populated

D1 40V DUAL SERIES SCHOTTKY BARRIER DIODE Reverse Power Protection

R11, R14, R21, R24 RESISTOR, SMD, 0603, 10kΩ, 1%, 1/16W, ROHS Gain Setting Resistor

R13, R23 RESISTOR, SMD, 0603, 100kΩ, 1%, 1/16W, ROHS Gain Setting Feedback Resistor

R1-R3, R5-R8, R10, R12, R15,

R17, R20, R22, R28-R30,

R32, R34-R36

RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable resistors - not populated

U1 (ISL28208FBZ) ISL28208FBZ, IC PRECISION LOW NOSIE JFET OP AMP, SOIC, ROHS

Application Note 1658

Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is

cautioned to verify that the Application Note or Technical Brief is current before proceeding.

For information regarding Intersil Corporation and its products, see www.intersil.com

AN1658.0

July 26, 2011

ISL28208SOICEVAL2Z Top View

Application Note 1658

4AN1658.0

July 26, 2011

ISL28208SOICEVAL2Z Schematic Diagram

OUT IN+ IN-IN+ NODE OUTIN- NODE

CLOSE TO DUT

1R29

R26

OPEN

0.01µF0.01µF

1R30 2

J21

21 R31

1R16

J23

J18

J24

J22

J20

J19

J17

21 R36

1R32 21 R34

1R35

21 R22

21 R19

21 R21

21 R20

C10

21 R8

21 R7

1R5

1R4 2

1R24

C2 C4

C3 C5

1J15

1J16

J11

J14

J12

J13

21 R27

21 R1

21 R25

21 R23

1R6

1R17

21 R2

21 R28

21 R14

21 R3

21 R18

21 R15

1R12

21 R10

1R13

21 R11

10k

100k

SOIC8

DNP

OPEN

DNP

OPEN

DNP

OPEN

DNP

OPEN

DNP

10k 100k

100k

10k

0 DNP

100k

1µF 1µF

VREF

V+V-

2GENERIC

PACK.

OUT A

OUT B

IN-A

IN+A

IN-B

IN+B

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