National Instruments NI 5731 Series Bedienungsanleitung

NI 5731/5732/5733/5734R User Guide

and Specifications

The NI 5731/5732/5733/5734 is a family of high-speed digitizer adapter modules designed to work in

conjunction with your NI FlexRIOFPGA module. This document contains signal information and

specifications for the NI 5731/5732/5733/5734R, which is composed of an NI FlexRIO FPGA module

and the NI 5731/5732/5733/5734. This document also contains tutorial sections that demonstrate how

to acquire data using a LabVIEW FPGA example VI and how to create and run your own LabVIEW

project with the NI 5731/5732/5733/5734R.

Note NI 5731/5732/5733/5734R refers to the combination of your NI 5731/5732/5733/5734

adapter module and your NI FlexRIO FPGA module. NI 5731/5732/5733/5734 refers to your

NI 5731/5732/5733/5734 adapter module only.

A description of each of the NI 5731/5732/5733/5734 devices is given below:

•NI 5731—2 analog input, 12-bit, 40 MS/s digitizer

•NI 5732—2 analog input, 14-bit, 80 MS/s digitizer

•NI 5733—2 analog input, 16-bit, 120 MS/s digitizer

•NI 5734—4 analog input, 16-bit, 120 MS/s digitizer

Contents

Electromagnetic Compatibility Guidelines.......................................................................................... 2

How to Use Your NI FlexRIO Documentation Set ............................................................................. 3

Front Panel and Connector Pinouts ..................................................................................................... 4

Block Diagram..................................................................................................................................... 6

NI 5731/5732/5733/5734 Component-Level Intellectual Property (CLIP)......................................... 7

Cables................................................................................................................................................... 8

Clocking............................................................................................................................................... 9

Using Your Device with a LabVIEW FPGA Example VI .................................................................. 10

Creating a LabVIEW Project and Running a VI on an FPGA Target................................................. 12

Specifications....................................................................................................................................... 15

Where to Go for Support ..................................................................................................................... 41

Appendix: Installing EMI Controls ..................................................................................................... 42

NI 5731/5732/5733/5734R User Guide and Specifications 2 ni.com

Note Before configuring your NI 5731/5732/5733/5734R, you must install the appropriate software

and hardware. Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for

installation instructions. Figure 1 shows an example of a properly connected NI FlexRIO device.

Figure 1. NI FlexRIO Device

Electromagnetic Compatibility Guidelines

This product was tested and complies with the regulatory requirements and limits for electromagnetic

compatibility (EMC) as stated in the product specifications. These requirements and limits are designed

to provide reasonable protection against harmful interference when the product is operated in its

intended operational electromagnetic environment.

This product is intended for use in industrial locations. There is no guarantee that harmful interference

will not occur in a particular installation, when the product is connected to a test object, or if the product

is used in residential areas. To minimize the potential for the product to cause interference to radio and

television reception or to experience unacceptable performance degradation, install and use this product

in strict accordance with instructions in the product documentation.

Furthermore, any changes or modifications to the product not expressly approved by National

Instruments could void your authority to operate it under your local regulatory rules.

Caution To ensure the specified EMC performance, you must install PXI EMC Filler Panels

(National Instruments part number 778700-01) in adjacent chassis slots. For more information about

installing PXI EMC filler panels in your system, refer to the Appendix: Installing EMI Controls

section of this document.

Caution To ensure the specified EMC performance, operate this product only with shielded cables

and accessories.

Caution To ensure the specified EMC performance, install the included snap-on ferrite bead

(National Instruments part number 711856-01) on any cable attached to the AUX I/O connector in

accordance with the instructions listed in the Appendix: Installing EMI Controls section.

Caution This product is sensitive to electrostatic discharge (ESD). To ensure the specified EMC

performance, follow the programming instructions listed at the end of the Using Your Device with a

LabVIEW FPGA Example VI and Creating a LabVIEW Project and Running a VI on an FPGA

Target sections of this document.

NI FlexRIO

Adapter Module + = NI FlexRIO Device

NI FlexRIO

FPGA Module

©National Instruments Corporation 3 NI 5731/5732/5733/5734R User Guide and Specifications

How to Use Your NI FlexRIO Documentation Set

Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set.

Figure 2. How to Use Your NI FlexRIO Documentation Set

Table 1. NI FlexRIO Documentation Locations and Descriptions

Document Location Description

NI FlexRIO FPGA

Module Installation

Guide and Specifications*

Available in your FPGA module

hardware kit and from the Start Menu.

Contains installation instructions for your

NI FlexRIO system and specifications for your

FPGA module.

NI xxxxR User Guide and

Specifications*

Available from the Start Menu. Contains signal information, examples, and

specifications for your adapter module.

LabVIEW FPGA Module

Help*

Embedded in LabVIEW Help.Contains information about the basic functionality of

LabVIEW FPGA Module.

NI FlexRIO Help*Embedded in LabVIEW FPGA

Module Help.

Contains FPGA module, adapter module, and CLIP

configuration information.

LabVIEW Examples Available in NI Example Finder. Contains examples of how to run FPGA VIs and

Host VIs on your device.

Other Useful Information on ni.com

ni.com/ipnet Contains LabVIEW FPGA functions and intellectual property to share.

ni.com/flexrio Contains product information and data sheets for NI FlexRIO devices.

* These documents are also available at ni.com/manuals.

LabVIEW FPGA

Module Help

NI FlexRIO

Help

LabVIEW

Examples

INSTALL Hardware

and Software

CONNECT Signals

and Learn About

Your Adapter

Module

LEARN About

LabVIEW FPGA

Module

PROGRAM Your

NI FlexRIO System

in LabVIEW FPGA

Module

NI FlexRIO FPGA Module

Installation Guide and Specifications

NI FlexRIO Adapter Module

User Guide and Specifications

Are

You New to

LabVIEW FPGA

Module?

Ye s N o

NI 5731/5732/5733/5734R User Guide and Specifications 4 ni.com

Front Panel and Connector Pinouts

Front Panel

Table 2 shows the front panel connector and signal descriptions for the NI 5731/5732/5733/5734. Refer

to the Specifications section of this document for additional signal information.

Table 2. NI 5731/5732/5733/5734 Front Panel Connectors

Connector Signal Description

AI 0 50 single-ended analog input channel 0.

AI 1 50 single-ended analog input channel 1.

AI 2 50 single-ended analog input channel 2 (NI 5734 only).

AI 3 50 single-ended analog input channel 3 (NI 5734 only).

CLK IN Reference or external clock input, 50 single-ended.

AUX I/O Refer to Table 3 for the signal list and descriptions.

AUX

I/O

AI 0

CLK IN

AI 1

NI 5732

INSTRUMENTS

NATIONAL

80 MS/s

Digitizer

AUX

I/O

AI 0

CLK IN

AI 1

NI 5731

INSTRUMENTS

NATIONAL

40 MS/s

Digitizer

AUX

I/O

AI 0

CLK IN

AI 1

NI 5733

INSTRUMENTS

NATIONAL

120 MS/s

Digitizer

AUX

I/O

AI 0

CLK IN

AI 1

AI 3

AI 2

NI 5734

INSTRUMENTS

NATIONAL

120 MS/s

Digitizer

©National Instruments Corporation 5 NI 5731/5732/5733/5734R User Guide and Specifications

Caution Connections that exceed any of the maximum ratings of any connector on the

NI 5731/5732/5733/5734 can damage the device and the chassis. NI is not liable for any damage

resulting from such signal connections. For the maximum input and output ratings for each signal,

refer to the Specifications section of this document.

AUX I/O Connector

Table 3 shows the pin assignments for the AUX I/O connector on the NI 5731/5732/5733/5734.

Caution The AUX I/O connector accepts a standard, third-party HDMI cable, but the AUX I/O port

is not an HDMI interface. Do not connect the AUX I/O port on the NI 5731/5732/5733/5734 into the

HDMI port of another device. NI is not liable for any damage resulting from such signal connections.

Table 3. NI 5731/5732/5733/5734 AUX I/O Connector Pin Assignments

AUX I/O Connector Pin Signal Signal Description

1 DIO Port 0 (0) Bidirectional single-ended digital I/O data channel.

2 GND Ground reference for signals.

3 DIO Port 0 (1) Bidirectional single-ended digital I/O data channel.

4 DIO Port 0 (2) Bidirectional single-ended digital I/O data channel.

5 GND Ground reference for signals.

6 DIO Port 0 (3) Bidirectional single-ended digital I/O data channel.

7 DIO Port 1 (0) Bidirectional single-ended digital I/O data channel.

8 GND Ground reference for signals.

9 DIO Port 1 (1) Bidirectional single-ended digital I/O data channel.

10 DIO Port 1 (2) Bidirectional single-ended digital I/O data channel.

11 GND Ground reference for signals.

12 DIO Port 1 (3) Bidirectional single-ended digital I/O data channel.

13 PFI 0 Bidirectional single-ended digital I/O data channel.

14 NC No connect.

15 PFI 1 Bidirectional single-ended digital I/O data channel.

16 PFI 2 Bidirectional single-ended digital I/O data channel.

17 GND Ground reference for signals.

18 +5V +5 V power (10 mA maximum).

19 PFI 3 Bidirectional single-ended digital I/O data channel.

NI 5731/5732/5733/5734R User Guide and Specifications 6 ni.com

Block Diagram

Figure 3 shows the NI 5731/5732/5733/5734 block diagram and signal flow to and from the

NI 5731/5732/5733/5734 component-level intellectual property (CLIP) by way of the adapter module

and the corresponding CLIP in LabVIEW FPGA.

Figure 3. NI 5731/5732/5733/5734 Connector Signals and CLIP Signal Block Diagram

NI 5731/5732/5733/5734 Adapter Module

AI 0

AI 2

DIO Port 0 (0)

DIO Port 0 (1)

DIO Port 0 (2)

DIO Port 0 (3)

DIO Port 1 (0)

DIO Port 1 (1)

DIO Port 1 (2)

DIO Port 1 (3)

PFI 0

PFI 1

PFI 2

PFI 3

AUX I/O

ADC

ADC Clock

ADC Data

Sample Clock

ADC

LabVIEW FPGA CLIP

ADC Clock

ADC Data

ADC

Interface

ADC

Interface

AI 0

AI 2

AI 0 Over Range

AI 2 Over Range

DC Over Voltage

SPI Device Select

SPI Read

SPI Write

SPI Write Data

SPI Address

SPI Idle

DIO Port 0 WE

DIO Port 0 Rd Data (0)

DIO Port 0 Wr Data (0)

DIO Port 0 Rd Data (1)

DIO Port 0 Wr Data (1)

DIO Port 0 Rd Data (2)

DIO Port 0 Wr Data (2)

DIO Port 0 Rd Data (3)

DIO Port 0 Wr Data (3)

DIO Port 1 Rd Data (0)

DIO Port 1 Wr Data (0)

DIO Port 1 Rd Data (1)

DIO Port 1 Wr Data (1)

DIO Port 1 Rd Data (2)

DIO Port 1 Wr Data (2)

DIO Port 1 Rd Data (3)

DIO Port 1 Wr Data (3)

DIO Port 1 WE

PFI 3 Wr Data

PFI <0..3> WE

PFI 3 Rd Data

PFI 1 Rd Data

PFI 1 Wr Data

PFI 2 Rd Data

PFI 2 Wr Data

PFI 0 Rd Data

PFI 0 Wr Data

User Data 1

User Command

User Command Commit

User Command Status

User Return

Initialization Done

User Error

User Command Idle

User Data 0

AI 1

AI 3

SPI Read Data

PLL Locked

Sync Clock

CLK IN

SPI Engine

Calibration

EEPROM

DAC SPI

ADC SPI

ADT7408

Temperature

Sensor

DAC

OUT1 OUT2

OUT4

CLK1

REF IN

AD9511

CLK2

SPI

VCXO

AC/DC

Gain

1, 2, 4x

Filters

AC/DC

Gain

1, 2, 4x

Filters

PLL Loop

Filter

Enable VCXO

Enable PLL

External Sample CLK

External Ref CLK

Channel Controls

Microcontroller

AI 1

AI 3

AI 1 Over Range

AI 3 Over Range

©National Instruments Corporation 7 NI 5731/5732/5733/5734R User Guide and Specifications

NI 5731/5732/5733/5734 Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes a feature for HDL IP integration called CLIP. NI FlexRIO

devices support two types of CLIP: user-defined and socketed.

•User-defined CLIP allows users to insert HDL IP into an FPGA target, enabling VHDL code to

communicate directly with an FPGA VI.

•Socketed CLIP provides the same IP integration functionality of the user-defined CLIP, but also

allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter module

socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external

adapter module connector interface.

Figure 4 shows the relationship between an FPGA VI and CLIP.

Figure 4. CLIP and FPGA VI Relationship

Adapter Module

CLIP Socket

LabVIEW

FPGA VI

User-Defined

CLIP

NI FlexRIO FPGA Module

FPGA

External

I/O Connector

Adapter

Module

Socketed

CLIP

User-Defined

CLIP Fixed I/O

DRAM 0

CLIP Socket

Socketed

CLIP

DRAM 1

CLIP Socket

Socketed

CLIP

Fixed I/O

DRAM0 DRAM1

NI 5731/5732/5733/5734R User Guide and Specifications 8 ni.com

The NI 5731/5732/5733/5734 ships with socketed CLIP items that are used to add module I/O to the

LabVIEW project.

The NI 5731/5732/5733/5734 CLIP items provides access to two analog input channels (four analog

input channels on the NI 5734), eight bidirectional DIO channels, four bidirectional PFI channels, and

an input clock selector that can be configured to use one of the following settings:

• Internal Sample clock

• Internal Sample clock locked to an external Reference clock through the CLK IN connector

• External Sample clock through the CLK IN connector

• Internal Sample clock locked to an external Reference clock through Sync Clock

The CLIP items also contain an engine to program the ADC and clock, either through predetermined

settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced

setup. In the LabVIEW FPGA Module, analog input data is accessed using a U16 data type (left

justified). The DIO signals are grouped into two ports of four signals each and are accessed using a U8

data type and Boolean write enable signal. The four PFI signals are accessed individually using

Booleans.

Refer to the NI FlexRIO Help for more information about NI FlexRIO CLIP items, configuring the

NI 5731/5732/5733/5734 with a socketed CLIP, and a list of available socketed CLIP signals.

Cables

• Use any shielded 50 coaxial cable of less than 3 meters in length with a BNC plug end to connect

to the AI 0, AI 1, AI 2, and AI 3 connectors on the NI 5731/5732/5733/5734 front panel.

• Use any shielded 50 coaxial cable of less than 3 meters in length with an SMB plug end to

connect to the CLK IN connector.

• Use any HDMI cable with the provided ferrite bead to connect to the digital I/O and PFI signals on

the AUX I/O connector.

Caution To ensure the specified EMC performance, install the included snap-on ferrite bead

(National Instruments part number 711856-01) on any cable attached to the AUX I/O connector in

accordance with the instructions listed in the Appendix: Installing EMI Controls section.

©National Instruments Corporation 9 NI 5731/5732/5733/5734R User Guide and Specifications

Clocking

The NI 5731/5732/5733/5734 clocks control the sample rate and other timing functions on the device.

Table 4 contains information about the possible NI 5731/5732/5733/5734 clock resources.

Note Specifications for the NI 5731/5732/5733/5734 adapter modules were characterized only at

the maximum sample rates.

Note For more information about configuring clocks, refer to the respective CLIP Help section for

your device in the NI FlexRIO Help.

Table 4. NI 5731/5732/5733/5734 Clock Sources

Clock

Configuration

Supported Sample

Rates

External

Clock

Type

External Clock

Frequency Description

Internal Clock

PLL Off

NI 5731 = 40 MS/s

NI 5732 = 80 MS/s

NI 5733 = 120 MS/s

NI 5734 = 120 MS/s

— — The internal VCXO

acts as a free-running

clock.

Internal Clock

PLL On

(IoModSyncClk)

NI 5731 = 40 MS/s

NI 5732 = 80 MS/s

NI 5733 = 120 MS/s

NI 5734 = 120 MS/s

—10 MHz The internal VCXO

locks to

IoModSyncClk (Sync

Clock), which is

provided only through

the backplane of

supported devices.

Internal Clock

PLL On

(CLK IN)

NI 5731 = 40 MS/s

NI 5732 = 80 MS/s

NI 5733 = 120 MS/s

NI 5734 = 120 MS/s

Reference

clock

10 MHz The internal VCXO

locks to an external

Reference clock,

which is provided

through the CLK IN

front panel connector.

External Clock

(CLK IN)

The supported

sample rate is equal

to the external clock

frequency.

Sample

clock

NI 5731 Min = 3 MHz

NI 5731 Max = 40 MHz

NI 5732 Min = 20 MHz*

NI 5732 Min = 10 MHz†

NI 5732 Max = 80 MHz

NI 5733 Min = 50 MHz

NI 5733 Max = 120 MHz

NI 5734 Min = 50 MHz

NI 5734 Max = 120 MHz

An external Sample

clock can be provided

through the CLK IN

front panel connector.

* Duty Cycle Stabilizer (DCS) enabled. DCS enabled is the default setting for all NI 5731/5732/5733/5734 CLIP items. You

can disable the DCS by adjusting register 9 in the ADC.

† DCS disabled.

NI 5731/5732/5733/5734R User Guide and Specifications 10 ni.com

Using Your Device with a LabVIEW FPGA Example VI

Note You must install the NI FlexRIO Adapter Module Support software before running this

example. Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for more

information about installing your software.

The NI FlexRIO Adapter Module Support software includes a variety of example projects to help get

you started creating your LabVIEW FPGA application. This section explains how to use an existing

LabVIEW FPGA example project to generate and acquire samples with the NI 5731/5732/5733/5734R.

This example requires at least one BNC cable for connecting signals to your device.

Note The examples available for your device are dependent on the version of the software and driver

you are using. For more information about which software versions are compatible with your device,

visit ni.com/info and enter rdsoftwareversion as the Info Code.

Each NI 5731/5732/5733/5734R example project includes the following components:

• A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware

• A VI that runs on Windows that interacts with the LabVIEW FPGA VI

Note In the LabVIEW FPGA Module software, NI FlexRIO adapter modules are referred to as

IO Modules.

Complete the following steps to run an example that acquires a waveform on AI 0 of the

NI 5731/5732/5733/5734.

1. Connect one end of an BNC cable to AI 0 on the front panel of the NI 5731/5732/5733/5734 and

the other end of the cable to your device under test (DUT).

2. Launch LabVIEW.

3. In the Getting Started window, click Find Examples to display the NI Example Finder.

4. In the NI Example Finder window, select Hardware Input and Output»FlexRIO»IO Modules»

NI 573X»NI 573y (where y represents the device number you are using).

5. Select NI 573y- Getting Started.lvproj. Wait for the project to finish opening.

6. In the Project Explorer window, open NI 573y- Getting Started (Host).vi under My Computer.

The host VI opens. The Open FPGA VI Reference function in this VI uses the NI 7952R as the

FPGA target by default. If you are using an NI FlexRIO FPGA module other than the NI 7952R,

complete the following steps to change to the FPGA VI to support your target.

a. Select Window»Show Block Diagram to open the VI block diagram.

b. On the block diagram, right-click the Open FPGA VI Reference (PXI-7952R) function and

select Configure Open FPGA VI Reference.

c. In the Configure Open FPGA VI Reference dialog box, click the Browse button next to the

Bitfile button.

d. In the Select Bitfile dialog box that opens, select the bitfile for your desired target. The bitfile

name is based on the adapter module, example type, and FPGA module.

e. Click the Select button.

f. Click OK in the Configure Open FPGA VI Reference dialog box.

g. Save the VI.

7. On the front panel, in the RIO Resource pull-down menu, select a resource that corresponds with

the target configured in step 6.

8. Select AI 0 in the AI Channel control.

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