NXP Semiconductors ADC1610S Series Bedienungsanleitung

Quick start ADC1610S series

(F1 or F2 versions)

Demonstration board for ADC1610S series

Rev. 5 —

January 2011

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Keywords

Abstract

Overview

Quick start ADC1610S series

(F1 or F2 versions)

Demonstration board for ADC1610S series

January 2011

Document information

Content

PCB2131-1, Demonstration board, ADC, Converter

This document describes how to use the demonstration board for the

analog-to-digital converter ADC1610Sseries.

Quick start ADC1610S series

Quick start

This document describes how to use the demonstration board for the

NXP Semiconductors

Quick start ADC1610S series (F1 or F2 versions)

Quick start

Revision history

Rev Date Description

1 20081001 Initial version.

2 20090518 Update

3 20090610 Add SPI software description.

4 20100519 Add HSDC extension module acquisition system description.

5 20110120 Update with latest software tool.

NXP Semiconductors

Quick start

Quick start ADC1610S series (F1 or F2 versions)

Quick start

Rev. 5 — January 2011

3 of

1. Overview of the ADC1610S demo board

1.1 ADC1610S F1 series (CMOS digital outputs)

Figure below presents the connections to measure ADC1610S.

Fig 1. 1.1 ADC1610S setup

programming

USB

SPI

DC adaptor

connected to

mains

LOGIC

ANALYZER

Output data

. DO (LSB) to Dxx

(MSB) . DAV for

synchro

. OTR Out of range

RESENTED CONFIGURATION

. 2V

input full scale

. Single Sine wave clock signal

. Input common mode from IC

. Binary ADC output

. SPI Mode

SYNTHESIZED

SIGNAL

GENERATOR

LOCK SIGNAL

. Sine wave

. AC

NPUT SIGNAL

. 2V

sine wave

. AC

SYNTHESIZED

SIGNAL

GENERATOR

ILTER

. High-order

. Band pass

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Rev. 5 — January 2011

4 of

1.2 ADC1610S F2

series (LVDS/DDR digital outputs)

Figure below presents the co

nnections to measure ADC

Fig 2. ADC1610S setup

LOCK SIGNAL

. Sine wave

. AC

SYNTHESIZED

SIGNAL

GENERATOR

USB

SPI

programming

NPUT SIGNAL

. 2V

sine wave

. AC

SYNTHESIZED

SIGNAL

GENERATOR

ILTER

. High-order

. Band pass

series (LVDS/DDR digital outputs)

nnections to measure ADC

1610S.

RESENTED CONFIGURATI

. 2V

input full scale

. Single Sine wave clock signal

. Input common mode from IC

. Binary ADC output

. SPI Mode

EXTENTION

MODULE

Data Acquisition

Optional module +

bridge

programming

DC adaptor

connected to

mains

NXP Semiconductors

Quick start

Quick start ADC1610S series (F1 or F2 versions)

RESENTED CONFIGURATI

input full scale

. Single Sine wave clock signal

. Input common mode from IC

. Binary ADC output

. SPI Mode

EXTENTION

MODULE

Data Acquisition

Optional module +

bridge

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1.3 Power supply

The board is powered either with a 3 V

adaptor.

Table 1. Power supply

Name Function

J8 2.1 Jack connector – 5VDC

hange ST9 and ST10 position accordingly

J10 +3V green connector –

Power supply 3 V

J11

Change ST9 and ST10 position accordingly

CMOS version

+1.8V green connector –

Power supply 1.8 V

LVDS DDR version

+3V green connector –

Power supply

TP1 GND test point

TP2 GND test point

1.4

Input signals (IN, CLK)

The input clock signal can be either a sine wave or a LVCMOS signal.

To ensure a good evaluation of the device, the input signal and the input clock must be

synchronized toge

Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should

follow the formula:

, where M is an odd number of period and N is the number of samples.

Quick start ADC1610S series (F1 or F2 versions)

Rev. 5 — January 2011

The board is powered either with a 3 V

and 1.8/3 V

power supplies or a 5V DC

View

hange ST9 and ST10 position accordingly

Power supply 3 V

Change ST9 and ST10 position accordingly

Power supply 1.8 V

Power supply

1.8 V

Input signals (IN, CLK)

The input clock signal can be either a sine wave or a LVCMOS signal.

To ensure a good evaluation of the device, the input signal and the input clock must be

synchronized toge

ther.

Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should

follow the formula:

, where M is an odd number of period and N is the number of samples.

J10 / J11

TP2

ST9/10

Quick start ADC1610S series (F1 or F2 versions)

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5 of 28

power supplies or a 5V DC

The input clock signal can be either a sine wave or a LVCMOS signal.

To ensure a good evaluation of the device, the input signal and the input clock must be

Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should

, where M is an odd number of period and N is the number of samples.

TP1

ST9/10

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Quick start ADC1610S series (F1 or F2 versions)

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Quick start Rev. 5 — January 2011 6 of 28

Table 2. Input signals

Name Function View

J1 IN connector – Analog input signal (

Ω

matching)

J2 CLKP connector – Single ended clock input signal (

Ω

matching), with a transformer.

J3 CLKM connector – Grounded on that demoboard

1.5 Output signals in CMOS version (D0 to D15, DAV, OTR)

The digital output signal is available in binary, 2’s complement or gray format.

A Data Valid Output clock (DAV) is provided by the device for the data acquisition.

Table 3.

Output signals

Name Function View

J6 Array connector – ADC digital output (D0 to D15), OTR

and Data Valid (DAV)

NXP Semiconductors

Quick start ADC1610S series (F1 or F2 versions)

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Quick start Rev. 5 — January 2011 7 of 28

1.6 Output signals in LVDS DDR version

The digital output signal is available in binary, 2’s complement or gray format.

A Data Valid Output clock (DAV) is provided by the device for the data acquisition.

Table 4.

Output signals

Name Function View

J7 Samtec QTH connector – ADC digital output (D0 to D15)

and Data Valid (DAV)

NXP Semiconductors

Quick start ADC1610S series (F1 or F2 versions)

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Quick start Rev. 5 — January 2011 8 of 28

1.7 SPI Mode

The ADC1610S can be controlled either by a Serial Peripheral Interface (SPI) or by PIN.

Table 5.

SPI Interface

Name Function View

J12 USB connector – SPI interface

1.8 SPI program

For more details on how to control device with SPI, refer to section 3.3.

J12

NXP Semiconductors

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Quick start ADC1610S series (F1 or F2 versions)

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Rev. 5 — January 2011

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2. HSDC extension module: acquisition board

The figure 4 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board:

Fig 3. HSDC extension module: acquisition board

+5V

OWER SUPPLY

. I = 3.2 A

EFERENCE SIGNAL

. Typical 10 MHz

SIGNAL

GENERATOR

USB

SPI

MODULE

RESENTED CONFIGURATION

. Acquisition board

. External reference signal

. LVDS DDR 16-bit input stream

. CMOS 2 16-bit channels input

LVDS

DDR

I/O

CONNECTOR

. Up to 325 MHz 16-bit LVDS DDR

CMOS

I/O

CONNECTOR

. 2 channels up to 200 MHz 16-bit

UMPER FOR

I/O

SUPPLY

. Define either I/O is 1.8 V or 3.3 V

RED LED

FOR POWER

SUPPLY CONNECTION

RED LED

FOR

+3V3

POWER

RED LED

FOR

USB

CONNECTION

GREEN LED FOR

EMBEDDED

PLL LOCK STATUS

FLASHING RED

FOR

FPGA STATUS

NXP Semiconductors

Quick start ADC1610S series (F1 or F2 versions)

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Quick start Rev. 5 — January 2011 10 of 28

The HSDC extension module is intended for acquisition/generation and clock generation

purpose. When connected to an ADC demo-board it is intended as an acquisition system

for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR

(SAMTEC QTH_060_02 P2 connector).

The board brief specification is shown below:

•32 MB memory size for acquisition pattern;

•2 16-bit channels CMOS up to 200 MHz;

•16-bit LVDS DDR input data stream up to 320 MHz;

•On-board or external reference for signal generation.

In this section the specific requirement for the use with ADC1610S demo-board will be

shown.

For more details on the HSDC-EXTMOD01/DB, please contact dataconverter-

support@nxp.com.

2.1 HSDC extension module: hardware initialization

Before using the generation board, make sure that you connect the USB cable prior to

the supply.

When USB and power cable are connected, the HSDC-EXTMOD will light 3 red LEDs.

The green LED close to the PLL is only when it is locked (see section 3.3).

The red LED close to FPGA reports normal behavior when flashing ¼ on, ¾ off. Any

other flashing behavior reports a failure at initialization (see section 3.3).

2.2 HSDC extension module: CMOS connector description

The figure 5 shows a brief description of the hardware connection on the HE14

connector.

For proper use of the acquisition board, make sure that resistor R86 (0 Ω) is connected

while R84 is removed.

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