NXP Semiconductors KL25 Series Bedienungsanleitung

KL25 Sub-Family Reference Manual

Supports: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4,

MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4,

MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4,

MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4

Document Number: KL25P80M48SF0RM

Rev. 3, September 2012

KL25 Sub-Family Reference Manual, Rev. 3, September 2012

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................33

1.1.1 Purpose.........................................................................................................................................................33

1.1.2 Audience......................................................................................................................................................33

1.2 Conventions..................................................................................................................................................................33

1.2.1 Numbering systems......................................................................................................................................33

1.2.2 Typographic notation...................................................................................................................................34

1.2.3 Special terms................................................................................................................................................34

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................35

2.2 Kinetis L Series.............................................................................................................................................................35

2.3 KL25 Sub-Family Introduction.....................................................................................................................................38

2.4 Module functional categories........................................................................................................................................39

2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................39

2.4.2 System Modules...........................................................................................................................................40

2.4.3 Memories and Memory Interfaces...............................................................................................................41

2.4.4 Clocks...........................................................................................................................................................41

2.4.5 Security and Integrity modules....................................................................................................................42

2.4.6 Analog modules...........................................................................................................................................42

2.4.7 Timer modules.............................................................................................................................................42

2.4.8 Communication interfaces...........................................................................................................................43

2.4.9 Human-machine interfaces..........................................................................................................................44

2.5 Orderable part numbers.................................................................................................................................................44

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................45

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3.2 Module to Module Interconnects..................................................................................................................................45

3.2.1 Module to Module Interconnects.................................................................................................................45

3.2.2 Analog reference options.............................................................................................................................48

3.3 Core Modules................................................................................................................................................................48

3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................48

3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................51

3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................55

3.4 System Modules............................................................................................................................................................56

3.4.1 SIM Configuration.......................................................................................................................................56

3.4.2 System Mode Controller (SMC) Configuration...........................................................................................57

3.4.3 PMC Configuration......................................................................................................................................57

3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................58

3.4.5 MCM Configuration....................................................................................................................................60

3.4.6 Crossbar-Light Switch Configuration..........................................................................................................61

3.4.7 Peripheral Bridge Configuration..................................................................................................................62

3.4.8 DMA request multiplexer configuration......................................................................................................63

3.4.9 DMA Controller Configuration...................................................................................................................66

3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................67

3.5 Clock Modules..............................................................................................................................................................70

3.5.1 MCG Configuration.....................................................................................................................................70

3.5.2 OSC Configuration......................................................................................................................................71

3.6 Memories and Memory Interfaces................................................................................................................................72

3.6.1 Flash Memory Configuration.......................................................................................................................72

3.6.2 Flash Memory Controller Configuration.....................................................................................................74

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3.6.3 SRAM Configuration...................................................................................................................................75

3.7 Analog...........................................................................................................................................................................77

3.7.1 16-bit SAR ADC Configuration..................................................................................................................77

3.7.2 CMP Configuration......................................................................................................................................81

3.7.3 12-bit DAC Configuration...........................................................................................................................83

3.8 Timers...........................................................................................................................................................................84

3.8.1 Timer/PWM Module Configuration............................................................................................................84

3.8.2 PIT Configuration........................................................................................................................................87

3.8.3 Low-power timer configuration...................................................................................................................88

3.8.4 RTC configuration.......................................................................................................................................90

3.9 Communication interfaces............................................................................................................................................91

3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................91

3.9.2 SPI configuration.........................................................................................................................................96

3.9.3 I2C Configuration........................................................................................................................................97

3.9.4 UART Configuration...................................................................................................................................98

3.10 Human-machine interfaces (HMI)................................................................................................................................99

3.10.1 GPIO Configuration.....................................................................................................................................99

3.10.2 TSI Configuration........................................................................................................................................101

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................105

4.2 System memory map.....................................................................................................................................................105

4.3 Flash Memory Map.......................................................................................................................................................106

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................106

4.4 SRAM memory map.....................................................................................................................................................107

4.5 Bit Manipulation Engine...............................................................................................................................................107

4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................108

4.6.1 Read-after-write sequence and required serialization of memory operations..............................................108

4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................109

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4.6.3 Modules Restricted Access in User Mode...................................................................................................112

4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................112

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................115

5.2 Programming model......................................................................................................................................................115

5.3 High-Level device clocking diagram............................................................................................................................115

5.4 Clock definitions...........................................................................................................................................................116

5.4.1 Device clock summary.................................................................................................................................117

5.5 Internal clocking requirements.....................................................................................................................................119

5.5.1 Clock divider values after reset....................................................................................................................119

5.5.2 VLPR mode clocking...................................................................................................................................120

5.6 Clock Gating.................................................................................................................................................................121

5.7 Module clocks...............................................................................................................................................................121

5.7.1 PMC 1-kHz LPO clock................................................................................................................................122

5.7.2 COP clocking...............................................................................................................................................122

5.7.3 RTC clocking...............................................................................................................................................123

5.7.4 LPTMR clocking..........................................................................................................................................123

5.7.5 TPM clocking...............................................................................................................................................124

5.7.6 USB FS OTG Controller clocking...............................................................................................................124

5.7.7 UART clocking............................................................................................................................................125

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................127

6.2 Reset..............................................................................................................................................................................127

6.2.1 Power-on reset (POR)..................................................................................................................................128

6.2.2 System reset sources....................................................................................................................................128

6.2.3 MCU Resets.................................................................................................................................................131

6.2.4 Reset Pin .....................................................................................................................................................133

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6.2.5 Debug resets.................................................................................................................................................133

6.3 Boot...............................................................................................................................................................................134

6.3.1 Boot sources.................................................................................................................................................134

6.3.2 FOPT boot options.......................................................................................................................................134

6.3.3 Boot sequence..............................................................................................................................................135

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................137

7.2 Clocking Modes............................................................................................................................................................137

7.2.1 Partial Stop...................................................................................................................................................137

7.2.2 DMA Wakeup..............................................................................................................................................138

7.2.3 Compute Operation......................................................................................................................................139

7.2.4 Peripheral Doze............................................................................................................................................140

7.2.5 Clock Gating................................................................................................................................................141

7.3 Power modes.................................................................................................................................................................141

7.4 Entering and exiting power modes...............................................................................................................................143

7.5 Module Operation in Low Power Modes......................................................................................................................143

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................149

8.2 Flash Security...............................................................................................................................................................149

8.3 Security Interactions with other Modules.....................................................................................................................149

8.3.1 Security Interactions with Debug.................................................................................................................150

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................151

9.2 Debug Port Pin Descriptions.........................................................................................................................................151

9.3 SWD status and control registers..................................................................................................................................152

9.3.1 MDM-AP Control Register..........................................................................................................................153

9.3.2 MDM-AP Status Register............................................................................................................................154

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9.4 Debug Resets................................................................................................................................................................156

9.5 Micro Trace Buffer (MTB)...........................................................................................................................................157

9.6 Debug in Low Power Modes........................................................................................................................................157

9.7 Debug & Security.........................................................................................................................................................157

Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................159

10.2 Signal Multiplexing Integration....................................................................................................................................159

10.2.1 Port control and interrupt module features..................................................................................................160

10.2.2 Clock gating.................................................................................................................................................161

10.2.3 Signal multiplexing constraints....................................................................................................................161

10.3 Pinout............................................................................................................................................................................161

10.3.1 KL25 Signal Multiplexing and Pin Assignments........................................................................................161

10.3.2 KL25 Pinouts...............................................................................................................................................164

10.4 Module Signal Description Tables................................................................................................................................168

10.4.1 Core Modules...............................................................................................................................................168

10.4.2 System Modules...........................................................................................................................................169

10.4.3 Clock Modules.............................................................................................................................................169

10.4.4 Memories and Memory Interfaces...............................................................................................................169

10.4.5 Analog..........................................................................................................................................................169

10.4.6 Timer Modules.............................................................................................................................................170

10.4.7 Communication Interfaces...........................................................................................................................171

10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................173

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................175

11.2 Overview.......................................................................................................................................................................175

11.2.1 Features........................................................................................................................................................175

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Section number Title Page

11.2.2 Modes of operation......................................................................................................................................176

11.3 External signal description............................................................................................................................................176

11.4 Detailed signal description............................................................................................................................................177

11.5 Memory map and register definition.............................................................................................................................177

11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................183

11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................185

11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................186

11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................186

11.6 Functional description...................................................................................................................................................187

11.6.1 Pin control....................................................................................................................................................187

11.6.2 Global pin control........................................................................................................................................188

11.6.3 External interrupts........................................................................................................................................188

Chapter 12

System integration module (SIM)

12.1 Introduction...................................................................................................................................................................191

12.1.1 Features........................................................................................................................................................191

12.2 Memory map and register definition.............................................................................................................................191

12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................193

12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................194

12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................195

12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................197

12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................199

12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................200

12.2.7 System Device Identification Register (SIM_SDID)...................................................................................202

12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................204

12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................206

12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................207

12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................209

12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................210

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12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................211

12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................213

12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................213

12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................214

12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................214

12.2.18 COP Control Register (SIM_COPC)...........................................................................................................215

12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................216

12.3 Functional description...................................................................................................................................................216

Chapter 13

System Mode Controller (SMC)

13.1 Introduction...................................................................................................................................................................217

13.2 Modes of operation.......................................................................................................................................................217

13.3 Memory map and register descriptions.........................................................................................................................219

13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................219

13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................221

13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................222

13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................223

13.4 Functional description...................................................................................................................................................224

13.4.1 Power mode transitions................................................................................................................................224

13.4.2 Power mode entry/exit sequencing..............................................................................................................227

13.4.3 Run modes....................................................................................................................................................229

13.4.4 Wait modes..................................................................................................................................................231

13.4.5 Stop modes...................................................................................................................................................232

13.4.6 Debug in low power modes.........................................................................................................................235

Chapter 14

Power Management Controller (PMC)

14.1 Introduction...................................................................................................................................................................237

14.2 Features.........................................................................................................................................................................237

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