NXP Semiconductors P89LPC980 Bedienungsanleitung

UM10346

LPC980/982 User manual

Rev. 01 — 2 November 2009 User manual

Document information

Info Content

Keywords P89LPC980/982

Abstract Technical information for the P89LPC980/982 device

User manual Rev. 01 — 2 November 2009 2 of 132

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors UM10346

LPC980/982 User manual

Revision history

Rev Date Description

01 20091102 Initial version.

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LPC980/982 User manual

1. Introduction

The P89LPC980/982 is a single-chip microcontroller, available in low cost packages,

based on a high performance processor architecture that executes instructions in two to

four clocks, six times the rate of standard 80C51 devices. Many system-level functions

have been incorporated into the P89LPC980/982 in order to reduce component count,

board space, and system cost.

1.1 Pin configuration

Fig 1. P89LPC980/982 TSSOP28 pin configuration

P89LPC980

P89LPC982

002aae536

P2.0/TXD

P2.1/RXD

P0.0/CMP2/KBI0/SPICLK

P1.7/T3EX/MOSI

P1.6/MISO

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1/T4EX/SS

P1.3/INT0/SDA/T4

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.7/SDA

P2.6/SCL

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3/T2

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5/T3

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD/T2EX

P2.5/SPICLK

P2.4/SS

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1.2 Pin description

Fig 2. P89LPC982 PLCC28 pin configuration

P89LPC982

002aae538

P1.6/MISO

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1/T4EX/SS

P1.3/INT0/SDA/T4

P1.7/T3EX/MOSI

P0.0/CMP2/KBI0/SPICLK

P2.1/RXD

P2.0/TXD

P2.7/SDA

P2.6/SCL

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3/T2

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5/T3

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P1.1/RXD/T2EX

P1.0/TXD

Table 1. Pin description

Symbol Pin Type Description

PLCC28,

TSSOP28

P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset

Port 0 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 0 pins as inputs and outputs depends upon the port

configuration selected. Each port pin is configured independently. Refer to Section

4.1 “Port configurations”for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

P0.0/CMP2/KBI0/

SPICLK 3I/OP0.0 — Port 0 bit 0.

OCMP2 — Comparator 2 output

IKBI0 — Keyboard input 0.

I/O SPICLK — SPI clock. When configured as master, this pin is output; when

configured as slave, this pin is input. (Pin Remap)

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P0.1/CIN2B/

KBI1 26 I/O P0.1 — Port 0 bit 1.

ICIN2B — Comparator 2 positive input B.

IKBI1 — Keyboard input 1.

P0.2/CIN2A/

KBI2 25 I/O P0.2 — Port 0 bit 2.

ICIN2A — Comparator 2 positive input A.

IKBI2 — Keyboard input 2.

P0.3/CIN1B/

KBI3/T2 24 I/O P0.3 — Port 0 bit 3. High current source.

ICIN1B — Comparator 1 positive input B.

IKBI3 — Keyboard input 3.

I/O T2 — Timer/counter 2 external count input or overflow output.

P0.4/CIN1A/

KBI4 23 I/O P0.4 — Port 0 bit 4. High current source.

ICIN1A — Comparator 1 positive input A.

IKBI4 — Keyboard input 4.

P0.5/CMPREF/

KBI5/T3 22 I/O P0.5 — Port 0 bit 5. High current source.

ICMPREF — Comparator reference (negative) input.

IKBI5 — Keyboard input 5.

I/O T3 — Timer/counter 3 external count input or overflow output.

Table 1. Pin description …continued

Symbol Pin Type Description

PLCC28,

TSSOP28

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P0.6/CMP1/KBI6 20 I/O P0.6 — Port 0 bit 6. High current source.

OCMP1 — Comparator 1 output.

IKBI6 — Keyboard input 6.

P0.7/KBI7/T1 19 I/O P0.7 — Port 0 bit 7. High current source.

I/O T1 — Timer/counter 1 external count input or overflow output.

IKBI7 — Keyboard input 7.

P1.0 to P1.7 I/O, I

[1] Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for

three pins as noted below. During reset Port 1 latches are configured in the input

only mode with the internal pull-up disabled. The operation of the configurable

Port 1 pins as inputs and outputs depends upon the port configuration selected.

Each of the configurable port pins are programmed independently. Refer to Section

4.1 “Port configurations”for details. P1.2 to P1.3 are open drain when used as

outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD 18 I/O P1.0 — Port 1 bit 0.

OTXD — Transmitter output for serial port.

P1.1/RXD/T2EX 17 I/O P1.1 — Port 1 bit 1.

IRXD — Receiver input for serial port.

IT2EX — Timer/counter 2 external capture input.

P1.2/SCL/T0 12 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O T0 — Timer/counter 0 external count input or overflow output. (open-drain when

used as output.)

I/O SCL — I2C-bus serial clock input/output.

P1.3/INT0/SDA/

T4 11 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

IINT0 — External interrupt 0 input.

I/O SDA — I2C-bus serial data input/output.

I/O T4 — Timer/counter 4 external count input or overflow output.

P1.4/INT1/T4EX/

SS 10 I/O P1.4 — Port 1 bit 4. High current source.

IINT1 — External interrupt 1 input.

IT4EX — Timer/counter 4 external capture input.

ISS — SPI Slave select . (Pin Remap)

P1.5/RST 6IP1.5 — Port 1 bit 5 (input only).

IRST — External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input, a LOW on this pin resets the microcontroller, causing

I/O ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force ISP mode.

P1.6/MISO 5 I/O P1.6 — Port 1 bit 6. High current source.

I/O MISO — SPI master in slave out. When configured as master, this pin is input,

when configured as slave, this pin is output. (Pin Remap)

Table 1. Pin description …continued

Symbol Pin Type Description

PLCC28,

TSSOP28

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P1.7/T3EX/MOSI 4 I/O P1.7 — Port 1 bit 7. High current source.

IT3EX — Timer/counter 3 external capture input.

I/O MOSI — SPI master out slave in. When configured as master, this pin is output;

when configured as slave, this pin is input. (Pin Remap)

P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset

Port 2 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 2 pins as inputs and outputs depends upon the port

configuration selected. Each port pin is configured independently. Refer to Section

4.1 “Port configurations”for details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0/TXD 1 I/O P2.0 — Port 2 bit 0.

OTXD — Transmitter output for serial port. (Pin Remap)

P2.1/RXD 2 I/O P2.1 — Port 2 bit 1.

IRXD — Receiver input for serial port. (Pin Remap)

P2.2/MOSI 13 I/O P2.2 — Port 2 bit 2.

I/O MOSI — SPI master out slave in. When configured as master, this pin is output;

when configured as slave, this pin is input.

P2.3/MISO 14 I/O P2.3 — Port 2 bit 3.

I/O MISO — SPI master in slave out.When configured as master, this pin is input,

when configured as slave, this pin is output.

P2.4/SS 15 I/O P2.4 — Port 2 bit 4.

ISS — SPI Slave select.

P2.5/SPICLK 16 I/O P2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master, this pin is output; when

configured as slave, this pin is input.

P2.6/SCL 27 I/O P2.6 — Port 2 bit 6.

I/O SCL — I2C-bus serial clock input/output. (Pin Remap)

P2.7/SDA 28 I/O P2.7 — Port 2 bit 7.

I/O SDA — I2C-bus serial data input/output. (Pin Remap)

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset

Port 3 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 3 pins as inputs and outputs depends upon the port

configuration selected. Each port pin is configured independently. Refer to Section

4.1 “Port configurations”for details.

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

P3.0/XTAL2/

CLKOUT 9I/OP3.0 — Port 3 bit 0.

OXTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is

selected via the flash configuration.

OCLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).

It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source

for the RTC/system timer.

Table 1. Pin description …continued

Symbol Pin Type Description

PLCC28,

TSSOP28

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[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P3.1/XTAL1 8 I/O P3.1 — Port 3 bit 1.

IXTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the flash configuration). It can be a port pin if internal RC oscillator or

watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not

used to generate the clock for the RTC/system timer.

VSS 7IGround: 0 V reference.

VDD 21 I Power supply: This is the power supply voltage for normal operation as well as

Idle and Power-down modes.

Table 1. Pin description …continued

Symbol Pin Type Description

PLCC28,

TSSOP28

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1.3 Logic symbols

(1) For Pin Remap.

Fig 3. P89LPC980/982 logic symbol

VDD VSS

PORT 0

PORT 3

TXD

RXD

INT0

INT1

RST

SCL

SDA

002aae534

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

XTAL2

XTAL1

KBI0SPICLK(1)

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

MOSI

MISO

SPICLK

PORT 1

T2EX

SCL(1)

SDA(1)

T4EX SS(1)

MOSI(1)

MISO(1)

T3EX

PORT 2

P89LPC980/982

TXD(1)

RXD(1)

CLKOUT

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1.4 Block diagram

Fig 4. P89LPC980/982 Block diagram

ACCELERATED 2-CLOCK 80C51 CPU

8 kB/4 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

clock

CONFIGURABLE

OSCILLATOR

ON-CHIP RC

OSCILLATOR

WITH CLOCK

DOUBLER

internal bus

POWER MANAGEMENT

(POWER-ON RESET,

BROWNOUT RESET,

REGULATORS)

002aae532

UART

ANALOG

COMPARATORS

256-BYTE

AUXILIARY RAM

(P89LPC982)

I2C-BUS

PORT 3

CONFIGURABLE I/Os

P89LPC980/982

WATCHDOG TIMER

AND OSCILLATOR

TIMER 0

TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

SPI

P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

TXD

RXD

SCL

SDA

CMP2

CIN2B

CIN2A

CMP1

CIN1A

CIN1B

TIMER 2

TIMER 3

TIMER 4

T2EX

T3EX

T4EX

SPICLK

MOSI

MISO

CRYSTAL

RESONATOR XTAL2

XTAL1

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