NXP Semiconductors LPC43Sxx Bedienungsanleitung

UM10503

LPC43xx/LPC43Sxx ARM Cortex-M4/M0 multi-core

microcontroller

Rev. 2.1 — 10 December 2015 User manual

Document information

Info Content

Keywords LPC43xx, LPC4300, LPC4370, LPC4350, LPC4330, LPC4320, LPC4310,

LPC4357, LPC4353, LPC4337, LPC4333, LPC4327, LPC4325, LPC4323,

LPC4322, LPC4317, LPC4315, LPC4313, LPC4312, LPC43S50, LPC43S30,

LPC43S20, LPC43S37, LPC43S57, LPC43S67, LPC4367, LPC43S70, ARM

Cortex-M4, ARM Cortex-M0, SPIFI, SCTimer/PWM, USB, Ethernet,

LPC4300 user manual, LPC43xx/LPC43Sxx user manual

Abstract LPC4300/LPC43S00 user manual

User manual Rev. 2.1 — 10 December 2015 2 of 1441

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LPC43xx/LPC43Sxx User manual

Revision history

Rev Date Description

2.1 20151210 LPC43xx/LPC43Sxx User manual

Modifications: •Added CREG1 register. See Table 98 “CREG1 register (CREG1, address 0x4004 3008) bit

description”.

•Updated text in Section 13.2.1 “Configuring the BASE_M4_CLK for high operating frequencies”: To

ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock

BASE_M4_CLK as described in Section 13.2.1.1.

•Updated description for USB0 (Event 9) and USB1(Event 10) peripheral in Table 83 “Event router

inputs”; USB0: Wake-up request signal. Not active in power-down and deep power-down mode. Use

for wake-up from sleep and deep-sleep mode; USB1: USB1 AHB_NEED_CLK signal. Not active in

power-down and deep power-down mode. Use for wake up from sleep and deep-sleep mode.

•Replaced Figure 15 “Boot process flowchart for LPC43xx parts with flash”with a new one.

2.0 20151104 LPC43xx/LPC43Sxx User manual

Modifications: •Updated keywords in Document information to add LPC436x and LPC 43S6x. See Table “Document

information”.

•Added text, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative

multiplier in Section 1.1 “Introduction”.

•Changed the title of each chapter to add LPC43Sxx.

•Updated ordering information table to add S parts. See Table 1 “Ordering information”.

•Updated ordering options table to add S-parts. See Table 2 “Ordering options”.

•Updated on-chip memory (parts with on-chip flash) list item in Section 1.2 “Features”: Upto 154 kB

SRAM for code and data use.

•Added block diagram of LPC436x/LPC43S6x. See Figure 5 “LPC436x/LPC43S6x block diagram

(parts with on-chip flash, dual-core)”

•Updated Table 10 “LPC43xx/LPC43Sxx SRAM configuration” to add LPC436x and LPC43S6x parts.

•Updated Figure 10 “Parts with on-chip flash: Memory mapping (overview)”.

•Added device and hex coding information for S parts to Table 46 “LPC43xx part identification

numbers”.

•Fixed CBC to read Cipher Block Chaining instead of Cipher Book Chaining in Section 8.2 “Features”.

•Updated Section 30.6 “Register description” text. Was REGMODEn = 1: Registers operate as match

and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0

and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.

REGMODEn = 1: Registers operate as capture and capture control registers.

•Updated Section 31.3 “Register description” text. Was REGMODEn = 1: Registers operate as match

and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0

and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.

REGMODEn = 1: Registers operate as capture and capture control registers.

•Updated Table 54 “IAP Copy RAM to Flash command”

Param1(SRC): Source internal SRAM address from which data bytes are to be read. This address

should be a word boundary.

•Fixed broken link in Section 11.4.13 “Cortex-M0SUB TXEV event clear register” and Section 11.4.14

“Cortex-M0APP TXEV event clear register”.

•Added a Remark to Section 25.9.1 “Endpoint queue head (dQH)”: In USB device control case if the

system error occurs, check if the endpoint transfer descriptor are programmed perfectly by software

application during set_configuration request. The system error will occur if the hardware accesses

inaccessible memory space for end point access.

•Changed the IAP command array size to 5: See Section 6.8 “IAP commands”.

Define data structure or pointers to pass the IAP command table and result table to the IAP function:

unsigned long command[5]; unsigned long result[5];

User manual Rev. 2.1 — 10 December 2015 3 of 1441

NXP Semiconductors UM10503

LPC43xx/LPC43Sxx User manual

•Updated Figure 24 “IAP parameter passing”.

•Updated Figure 27 “Boot flow for encrypted images (flashless parts)”.

•Removed tge GPCLEAR_ENx bits from the register description. See Table 917 “Event

Monitor/Recorder Control Register (ERCONTRO, address 0x4004 6084) bit description”.

•Updated Table 1059 “CAN message interface message control registers (IF1_MCTRL, address

0x400E 2038 (C_CAN0) and 0x400A 4038 (C_CAN1)) bit description”: bit descriptions for bit 11 TXIE

is: 0 = The INTPND bit will be left unchanged after a successful transmission of a frame. 1 = INTPND

will be set after a successful transmission of a frame.

•In Table 118 “Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit

description”, the value of Deep power down mode is changed to 0x0033 FF7F.

•In Table 20 “OTP function allocation”, updated otp_ProgUSBID: otp_ProgUSBID will program prod_id

and vend_id in word 1 of bank 3: 3; word 1.

•Added a table note to Table 986 “SPI clocking and power control”:

BASE_SPI_CLK 0.5 * BASE_M4_CLK (if interrupt goes to M4 or M0APP).

BASE_SPI_CLK 0.5 * BASE_PERIPH_CLK (if interrupt goes to M0SUB).

•In Table 42 “ISP Go command”, updated the address description and example: This address must be

on a word boundary and it is not allowed to add the Thumb bit (bit 0) of the address. The example is

G 436208208 T<CR><LF>" branches to address 0x1A00 0250.

•Updated Table 24 “Boot image header description”: Reserved bits: 15: 8 instead of 15:14.

•Updated Table 74 “Boot image header description”: AES_CONTROL bits: 15:8. added a remark

before the table.

•Re-named Part ID register to CHIP ID register: Table 96 “Register overview: Configuration registers

(base address 0x4004 3000)” and Table 107 “Chip ID register (CHIPID, address 0x4004 3200) bit

description”. Added CHIP ID for Flash devices Rev A: CHIP ID is 0x7906 002B to Table 107 “Chip ID

•Added SBUSCFG register. See Table 463 “System bus interface configuration register (SBUSCFG -

address 0x4000 6090) bit description”. Added a remark in Section 25.6.10 “Burst Size register

(BURSTSIZE)”.

•Updated Figure 32 “AES endianness”.

•Added a bullet to Section 6.2 “Basic configuration”. If the application uses the IAP interface, it must

reserve the SRAM space used by IAP as outlined in Section 6.4.5.8 “RAM used by IAP command

handler”.

•Updated Section 6.4.5.8 “RAM used by IAP command handler”. Added text: 16 B of RAM from

0x10089FF0 to 0x10089FFF. Applications making use of IAP calls must reserve this RAM block.

•Updated Section 6.4.5.7 “RAM used by ISP”; removed command handler from the title and updated

text.

Revision history …continued

Rev Date Description

User manual Rev. 2.1 — 10 December 2015 4 of 1441

NXP Semiconductors UM10503

LPC43xx/LPC43Sxx User manual

1.9 20150218 LPC43xx User manual

•Table 777 “SCT configuration example” updated and moved to Chapter 31.

•Number of EMC_CS and EMC_DYCS pins corrected for the LQFP208 pin package in Table 409

“EMC pinout for different packages”.

•Section 40.7.5.1 “USART clock in synchronous mode” added.

•Bit 12 changed to 1 for EMC address mapping 256 Mb, 512 Mb, 1 Gb. See Table 433 “Address

mapping”.

•Bit description of bits TSEG1 and TSEG2 corrected in Table 1037 “CAN bit timing register (BT,

address 0x400E 200C (C_CAN0) and 0x400A 400C (C_CAN1)) bit description” and Figure 170 “Bit

timing” updated for clarity.

•Parts MX1635E, W25Q16DV, W25Q32FV added to Table 25 “QSPI devices supported by the boot

code and the SPIFI API”.

•Use of IAP calls clarified: IAP commands are not supported for flash-less parts. See Section 6.8 “IAP

commands”.

•For flashless parts only: Unique part ID is stored in OTP bank 0 and readable at memory locations

0x4004 5000.to 0x4004 500C. See Section 4.1 and Table 14 “OTP memory description (OTP base

address 0x4004 5000)”.

•For secure parts only: Chapter 7 “LPC43Sxx Boot ROM for secure parts” added.

•For secure parts only: AES DMA request lines added. See Table 100, Table 330, and Table 350.

•Boot ROM chapter split into two chapters for secure and non-secure parts. See Chapter 5 “LPC43xx

Boot ROM” and Chapter 7 “LPC43Sxx Boot ROM for secure parts”.

•Section 5.1.1 “Determine the boot code version” added.

•Signal polarity of signals EMC_CKEOUT and EMC_DQMOUT corrected in Table 412 “EMC pin

description”. Both signals are active HIGH.

•IRC accuracy corrected in Section 1.2 “Features”.

•Added text: The secure boot from USART3 is not supported for LPC43Sxx parts: see Section 5.1,

Section 7.1, Table 21, and Table 22.

Revision history …continued

Rev Date Description

User manual Rev. 2.1 — 10 December 2015 5 of 1441

NXP Semiconductors UM10503

LPC43xx/LPC43Sxx User manual

Modifications: •Section 1.7 “ARM core features” added.

•ARM Cortex-M0 debug features added. See Section 51.3.

•Corrected remark for bits MODE3, RFCLK, and FBCLK in Table 447 “SPIFI control register (CTRL,

address 0x4000 3000) bit description”: MODE3, RFCLK, and FBCLK should not all be 1, because in

this case there is no final falling edge on SCK on which to sample the last data bit of the frame.

•RTCX2 TFBGA ball corrected: ball A7 changed to B7.

•Bit 4 changed from Reserved to SEE (System Error Enable) register USBINTR_D and USBINTR_H.

See Table 472 and Table 473.

•Bit 4 changed from Reserved to SEI in register USBSTS_D and USBSTS_H. See Table 470 and

Table 471.

•Bit 4 changed from Reserved to SEE in register USBINTR_D and USBINTR_H. See Table 533 and

Table 534.

•Bit 4 changed from Reserved to SEI register USBSTS_D and USBSTS_H. See Table 531 and

Table 532.

•Added Section 25.11, System error.

•Removed BUS_RST from Table 168.

•Updated Figure 8: the area specifying memory range 0x1008A000-0x10092000 is changed to 32 kB

local SRAM (LPC4370/50/30).

•Updated LPC43xx part identification number for LPC4370FET256 to0x0000 0030. See Table 46.

•Added a remark on how to read the FLADJ register in Section 11.4.15 and Section 11.4.16.

•Changed P1_13 from ball D6 to L8, P7_5 from ball C7 to A7, PF_4 from ball L8 to D6, RESET from

ball B7 to C7, RTCX2 moved from ball A7 to B7, and Ball G10 changed from VSS to VDDIO. See

Table 184.

Revision history …continued

Rev Date Description

User manual Rev. 2.1 — 10 December 2015 6 of 1441

NXP Semiconductors UM10503

LPC43xx/LPC43Sxx User manual

1.8 20140128 LPC43xx User manual

Modifications: •Description of the C_CAN CLKDIV register corrected. See Table 1073.

•Priorities of the EMC SDRAM ports added. See Section 22.4.

•Table 20 “OTP function allocation” corrected.

•Table 12 “OTP bank programming API functions available in ROM” added.

•Bit field width of bits LEVEL in the FIFO_STS and bits FIFO_LEVEL in the FIFO_CFG register

changed to 4 bits. See Table 1120 and Table 1121. Description of the FIFO_STS register updated to

explain the use of the LEVEL bits. See Table 1120.

•Condition for the CAN PCLK added: PCLK < 50 MHz. See Section 44.2.

•VBUS connection requirement for self-powered USB0 added to Section 24.5.1 “Requirements for

connecting the USB0_VBUS/USB1_VBUS signal”.

•SRAM memory location retained in Power-down mode clarified in Section 3.3.5 “Memory retention in

the Power-down modes” and Figure 6 “Flashless parts: System memory map (see Figure 7 for

detailed addresses of all peripherals)”.

•Section 36.7.1 “Register read procedure” updated for reading the RTC registers after wake-up.

•RTC_ALARM pin description corrected (Table 871 “RTC pin description”). This pin is not a 1.8 V pin.

•Part LPC4350FBD208 removed.

•Read-only status bits for EMC clock divider register configuration register added. See Table 161

“CCU1 branch clock configuration register (CLK_M4_EMCDIV_CFG, addresses 0x4005 1478) bit

description”.

•Description of the WAKEUP bits expanded in the CCU branch clock configuration and status

registers. See Section 13.5.3 “CCU1/2 branch clock configuration registers” and Section 13.5.4

“CCU1/2 branch clock status registers”.

•Bit RUN_N added to CCU branch clock status registers. See Section 13.5.3 “CCU1/2 branch clock

configuration registers”.

•Statement added: Only write to the RTC registers when the 32 kHz oscillator is running. See

Section 36.2. Same for Alarm timer. See Section 35.2.

•MII availability clarified: Ethernet MII not available on LQFP144 and TFBGA100 parts. See

Section 27.1 “How to read this chapter”.

•Timer input and output connections clarified in Section 31.2 and Figure 39 “Connections between

GIMA and peripherals”.

•Section 44.7.5.2 “Calculating the C_CAN bit rate” added.

Revision history …continued

Rev Date Description

User manual Rev. 2.1 — 10 December 2015 7 of 1441

NXP Semiconductors UM10503

LPC43xx/LPC43Sxx User manual

1.7 20131017 LPC43xx User manual

Modifications: •12-bit ADC (ADCHS) for parts LPC4370 added. See Chapter 47.

•Table “LPC43xx part identification numbers” updated.

•BASE_APLL_CLK renamed to BASE_AUDIO_CLK in Chapter 12 “LPC43xx Clock Generation Unit

(CGU)”, Chapter 13 “LPC43xx Clock Control Unit (CCU)”, Chapter 10 “LPC43xx Configuration

Registers (CREG)”, and Chapter 43 “LPC43xx I2S interface”.

•Core M0SUB added for parts LPLC4370. See Chapter 2 “LPC43xx Multi-Core configuration and

Inter-Process Communication (IPC)”, Chapter 12 “LPC43xx Clock Generation Unit (CGU)”,

Chapter 13 “LPC43xx Clock Control Unit (CCU)”, Chapter 10 “LPC43xx Configuration Registers

(CREG)”, Chapter 14 “LPC43xx Reset Generation Unit (RGU)”, and Chapter 3 “LPC43xx Memory

mapping”.

•Power-down mode with M0SUB SRAM maintained added for parts LPC4370. See Chapter 11

“LPC43xx Power Management Controller (PMC)” and Table 115.

•AES speed corrected.

•Bit description of register CREG5 corrected. Bits 9:0 changed to reserved. Use bits 12:10 for

disabling JTAG. See Section 10.4.3 “CREG5 control register”.

•Description of the RESET pin updated in Section 15.2 “Pin description”.

•Use of EMC_CLK pins clarified for SDRAM devices. See Section 22.2.

•Pin description of the RESET pin updated.

•Pin description of pins SD_VOLTD[2:0] updated.

•Add bits 20 (BOD reset) and 21 (reset after wake-up from deep power-down) to the event router

registers.

•Table 200 “SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description” added.

•USB driver code listing corrected. See Section 26.5 “USB API”.

•Register RESET_EXT_STAT4 removed.

•SDRAM address mappings added.

•Device MX25L6435EM2I-10G added to Table 24 “QSPI devices supported by the boot code and the

SPIFI API”.

•Table 4 “Ordering options” corrected. ULPI not available on 144-pin and 100-pin packages.

•Editorial updates to Section 5.3.5 “Boot image creation” and Figure 16 “Image encryption flow”

added.

•Editorial edits to Chapter 7 “LPC43xx Security API”. Section “CMAC using AES hardware

acceleration” removed.

•VADC replaced by ADCHS throughout the document.

•Section 12.2.1 “Configuring the BASE_M4_CLK for high operating frequencies” corrected to ensure

safe operation of the clock ramping procedure.

•Figures and tables in Section 43.7.2 “I2S operating modes” corrected.

Revision history …continued

Rev Date Description

User manual Rev. 2.1 — 10 December 2015 8 of 1441

NXP Semiconductors UM10503

LPC43xx/LPC43Sxx User manual

Modifications: •LPC4320 and LPC4310 part IDs corrected. See Table 45 “LPC43xx part identification numbers” and

the LPC4350/30/20/10 errata sheet.

•Description of word1 of the part id corrected. See Table 45 “LPC43xx part identification numbers”.

•General description of the OTP updated.

•General description of the AES updated.

•Figure 14 “Boot process for parts without flash” updated.

•Figure 115 “Repetitive Interrupt Timer (RIT) block diagram” corrected.

•Details about encryption of the image header added in Section 5.3.4 “Boot image header format”.

•Figure 14 “Boot process for parts without flash” corrected. SPI(SSP) boot requires image header.

•Bit description of Table 378 “Debounce Count Register (DEBNCE, address 0x4000 4064) bit

description” updated. Host clock is the SD_CLK clock.

•Security features updates. FIPS compliancy added.

•ISP mode added to Figure 14 “Boot process for parts without flash”.

•Reset values of the EEPROM RWSTATE and WSTATE registers updated.

•AES API function offsets corrected.

•Part MX25L8006EM2L-12GMX25L8035E, MX25L1633E, MX25L3235E, MX25L6435E,

MX25L12835F, MX25L25635F added to list of devices supported for SPIFI boot.

1.6 20130125 LPC43xx user manual.

Modifications: •SGPIO-DMA connections clarified.

•SGPIO location corrected.

•SGPIO added to DMA master 0.

•GPIO group interrupt wake-up from power-down modes corrected. Only wake-up from sleep mode

supported.

•Section “Supported QSPI devices” moved to Chapter “LPC43xx Boot ROM”.

•SPIFI register map and register descriptions added in Chapter “LPC43xx SPI Flash Interface

(SPIFI)”.

•Bit description of Table “CAN error counter (EC, address 0x400E 2008 (C_CAN0) and 0x400A 4008

(C_CAN1)) bit description” corrected.

•Bit clock calculation and bit description corrected in Section “CAN bit timing register”.

Revision history …continued

Rev Date Description

User manual Rev. 2.1 — 10 December 2015 9 of 1441

NXP Semiconductors UM10503

LPC43xx/LPC43Sxx User manual

1.5 20121203 LPC43xx user manual.

Modifications •Statement regarding the connection between sampling pin P2_7 and the watchdog timer overflow bit

is incorrect and was removed in Section “Sampling of pin P2_7” and Figure “Boot process flowchart

for LPC43xx parts with flash”.

•SCT alias register locations corrected.

•IRC accuracy corrected for flash-based parts.

•SCT with dither engine added for flash-based parts.

•SGPIO DMA connections added in Table “DMA mux control register (DMAMUX, address 0x4004

311C) bit description”.

•Section “MAC Frame filter register” updated to include hash filter option.

•Section “Hash filter” with examples added.

•Description of the I2C MASK register clarified.

•Description of the I2C slave address updated.

•UART1 TER register location and bit description corrected.

•Polarity of the DMACSYNC bit in the GPDMA SYNC register corrected.

•SGPIO pattern match example corrected.

•OTP API function table corrected. Location 0x1C is reserved.

•SPIFI data rate and maximum clock corrected to SPIFI_CLK = 104 MHz and 52 MB/s.

•Parts LPC433x, LPC432x, and LPC431x added.

•The following changes were made on the TFBGA180 pinout:

–P1_13 moved from ball D6 to L8.

–P7_5 moved from ball C7 to A7.

–PF_4 moved from ball L8 to D6.

–RESET moved from ball B7 to C7.

–RTCX2 moved from ball A7 to B7.

–Ball G10 changed from VSS to VDDIO.

•Section “JTAG TAP Identification” updated.

•EMC Configuration register, bit 8 changed to reserved. See Table “EMC Configuration register

(CONFIG - address 0x4000 5008) bit description”.

•Dual-core power-down modes added to Chapter “LPC43xx Power Management Controller (PMC)”.

Revision history …continued

Rev Date Description

User manual Rev. 2.1 — 10 December 2015 10 of 1441

NXP Semiconductors UM10503

Chapter :

Modifications: •ETM time stamping feature not implemented.

•Bit 0 in the RGU RESET_STATUS0 register changed to reserved. Section “Determine the cause of a

core reset” added.

•Micron part N25Q256 removed from the list of devices supported by the SPIFI boot ROM driver and

API. (See Table “QSPI devices not supported by the boot code”.)

•Part S25FL129P0XNFI01 added to the list of devices supported by the SPIFI boot ROM driver.

•SGPIO register descriptions for CTRL_ENABLED and CTRL_DISABLED registers updated.

•Section “Dynamic Memory Refresh Timer register” register description updated.

•Description of the Motor control PWM INVDC bit updated in Table “MCPWM Control read address

(CON - 0x400A 0000) bit description”.

•Description of the Alarm timer PRESETVAL bit updated in Table “Preset value register (PRESET -

0x4004 0004) bit description”.

•Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to

ADC0 and ADC1.

•Description of extra status bits added to Table “DMA Status register (DMA_STAT, address 0x4001

1014) bit description”.

•Use of lower SPIFI memory clarified in Table “SPIFI flash memory map”.

•Description of DAC DMA_ENA bit clarified in Table “D/A Control register (CTRL - address

0x400E 1004) bit description”.

•Pseudo-code for PLL registers updated by code snippets from LPC43xx sample code.

•Reset delay clock cycles explained in Section “RGU reset control register”.

1.4 20120903 LPC43xx user manual.

Modifications: •SSP0 boot pin functions corrected. Pin P3_3 = SSP0_SCK, pin P3_6 = SSP0_SSEL, pin P3_7 =

SSP0_MISO, pin P3_8 = SSP0_MOSI.

•CLKMODE3 removed from the SCT. Bit value CLKMODE = 0x3 changed to reserved “SCT

configuration register (CONFIG - address 0x4000 0000) bit description”.

•SWD mode removed for ARM Cortex-M0.

•Details for GIMA clock synchronization added.

•RESET_EXT_STATUS0 register removed.

•Reset value of BASE_SAFE_CLK register changed to R (read-only).

•Reset delay values corrected in Figure “RGU Reset structure”.

•RGU reset values corrected in Table “Register overview: RGU (base address: 0x4005 3000)”.

•Editorial updates in Chapter “LPC43xx Serial GPIO (SGPIO)”.

•POR reset value of the event router STATUS register corrected.

•USB boot mode updated: 12 MHz external crystal required.

•IAP invoke call entry pointer clarified.

•EMC memory data and control lines clarified for the LQFP208 package.

•Figure updated to include boot process for AES capable parts.

•Editorial updates.

Revision history …continued

Rev Date Description

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