NXP Semiconductors Freescale K30 Series Bedienungsanleitung

K30 Sub-Family Reference Manual

Supports: MK30DN512ZVLK10, MK30DN512ZVMB10

Document Number: K30P81M100SF2RM

Rev. 6, Nov 2011

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

2 Freescale Semiconductor, Inc.

Contents

Section Number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................51

1.1.1 Purpose.........................................................................................................................................................51

1.1.2 Audience......................................................................................................................................................51

1.2 Conventions..................................................................................................................................................................51

1.2.1 Numbering systems......................................................................................................................................51

1.2.2 Typographic notation...................................................................................................................................52

1.2.3 Special terms................................................................................................................................................52

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................53

2.2 K30 Family Introduction...............................................................................................................................................53

2.3 Module Functional Categories......................................................................................................................................53

2.3.1 ARM Cortex-M4 Core Modules..................................................................................................................54

2.3.2 System Modules...........................................................................................................................................55

2.3.3 Memories and Memory Interfaces...............................................................................................................56

2.3.4 Clocks...........................................................................................................................................................57

2.3.5 Security and Integrity modules....................................................................................................................57

2.3.6 Analog modules...........................................................................................................................................57

2.3.7 Timer modules.............................................................................................................................................58

2.3.8 Communication interfaces...........................................................................................................................59

2.3.9 Human-machine interfaces..........................................................................................................................60

2.4 Orderable part numbers.................................................................................................................................................60

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................61

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 3

Section Number Title Page

3.2 Core modules................................................................................................................................................................61

3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................61

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................64

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................70

3.2.4 JTAG Controller Configuration...................................................................................................................71

3.3 System modules............................................................................................................................................................72

3.3.1 SIM Configuration.......................................................................................................................................72

3.3.2 Mode Controller Configuration...................................................................................................................73

3.3.3 PMC Configuration......................................................................................................................................73

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................74

3.3.5 MCM Configuration....................................................................................................................................76

3.3.6 Crossbar Switch Configuration....................................................................................................................76

3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................78

3.3.8 Peripheral Bridge Configuration..................................................................................................................81

3.3.9 DMA request multiplexer configuration......................................................................................................83

3.3.10 DMA Controller Configuration...................................................................................................................86

3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................87

3.3.12 Watchdog Configuration..............................................................................................................................88

3.4 Clock Modules..............................................................................................................................................................89

3.4.1 MCG Configuration.....................................................................................................................................89

3.4.2 OSC Configuration......................................................................................................................................90

3.4.3 RTC OSC configuration...............................................................................................................................91

3.5 Memories and Memory Interfaces................................................................................................................................91

3.5.1 Flash Memory Configuration.......................................................................................................................91

3.5.2 Flash Memory Controller Configuration.....................................................................................................94

3.5.3 SRAM Configuration...................................................................................................................................95

3.5.4 SRAM Controller Configuration.................................................................................................................98

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

4 Freescale Semiconductor, Inc.

Section Number Title Page

3.5.5 System Register File Configuration.............................................................................................................99

3.5.6 VBAT Register File Configuration..............................................................................................................100

3.5.7 EzPort Configuration...................................................................................................................................100

3.6 Security.........................................................................................................................................................................102

3.6.1 CRC Configuration......................................................................................................................................102

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 5

Section Number Title Page

3.7 Analog...........................................................................................................................................................................102

3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................102

3.7.2 CMP Configuration......................................................................................................................................110

3.7.3 12-bit DAC Configuration...........................................................................................................................112

3.7.4 VREF Configuration....................................................................................................................................113

3.8 Timers...........................................................................................................................................................................114

3.8.1 PDB Configuration......................................................................................................................................114

3.8.2 FlexTimer Configuration.............................................................................................................................117

3.8.3 PIT Configuration........................................................................................................................................121

3.8.4 Low-power timer configuration...................................................................................................................122

3.8.5 CMT Configuration......................................................................................................................................124

3.8.6 RTC configuration.......................................................................................................................................125

3.9 Communication interfaces............................................................................................................................................126

3.9.1 CAN Configuration......................................................................................................................................126

3.9.2 SPI configuration.........................................................................................................................................128

3.9.3 I2C Configuration........................................................................................................................................131

3.9.4 UART Configuration...................................................................................................................................132

3.9.5 SDHC Configuration....................................................................................................................................134

3.9.6 I2S configuration..........................................................................................................................................135

3.10 Human-machine interfaces (HMI)................................................................................................................................137

3.10.1 GPIO configuration......................................................................................................................................137

3.10.2 TSI Configuration........................................................................................................................................138

3.10.3 Segment LCD Configuration.......................................................................................................................140

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................143

4.2 System memory map.....................................................................................................................................................143

4.2.1 Aliased bit-band regions..............................................................................................................................144

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

6 Freescale Semiconductor, Inc.

Section Number Title Page

4.3 Flash Memory Map.......................................................................................................................................................145

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................146

4.4 SRAM memory map.....................................................................................................................................................146

4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................146

4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................147

4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................151

4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................155

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................157

5.2 Programming model......................................................................................................................................................157

5.3 High-Level device clocking diagram............................................................................................................................157

5.4 Clock definitions...........................................................................................................................................................158

5.4.1 Device clock summary.................................................................................................................................159

5.5 Internal clocking requirements.....................................................................................................................................160

5.5.1 Clock divider values after reset....................................................................................................................161

5.5.2 VLPR mode clocking...................................................................................................................................162

5.6 Clock Gating.................................................................................................................................................................162

5.7 Module clocks...............................................................................................................................................................162

5.7.1 PMC 1-kHz LPO clock................................................................................................................................164

5.7.2 WDOG clocking..........................................................................................................................................164

5.7.3 Debug trace clock.........................................................................................................................................165

5.7.4 PORT digital filter clocking.........................................................................................................................165

5.7.5 LPTMR clocking..........................................................................................................................................166

5.7.6 FlexCAN clocking.......................................................................................................................................166

5.7.7 UART clocking............................................................................................................................................167

5.7.8 SDHC clocking............................................................................................................................................167

5.7.9 I2S clocking.................................................................................................................................................167

5.7.10 TSI clocking.................................................................................................................................................168

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 7

Section Number Title Page

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................171

6.2 Reset..............................................................................................................................................................................171

6.2.1 Power-on reset (POR)..................................................................................................................................172

6.2.2 System resets................................................................................................................................................172

6.2.3 Debug resets.................................................................................................................................................175

6.3 Boot...............................................................................................................................................................................177

6.3.1 Boot sources.................................................................................................................................................177

6.3.2 Boot options.................................................................................................................................................177

6.3.3 FOPT boot options.......................................................................................................................................177

6.3.4 Boot sequence..............................................................................................................................................178

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................181

7.2 Power modes.................................................................................................................................................................181

7.3 Entering and exiting power modes...............................................................................................................................183

7.4 Power mode transitions.................................................................................................................................................184

7.5 Power modes shutdown sequencing.............................................................................................................................185

7.6 Module Operation in Low Power Modes......................................................................................................................185

7.7 Clock Gating.................................................................................................................................................................188

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................189

8.2 Flash Security...............................................................................................................................................................189

8.3 Security Interactions with other Modules.....................................................................................................................190

8.3.1 Security Interactions with EzPort................................................................................................................190

8.3.2 Security Interactions with Debug.................................................................................................................190

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

8 Freescale Semiconductor, Inc.

Section Number Title Page

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................191

9.1.1 References....................................................................................................................................................193

9.2 The Debug Port.............................................................................................................................................................193

9.2.1 JTAG-to-SWD change sequence.................................................................................................................194

9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................194

9.3 Debug Port Pin Descriptions.........................................................................................................................................195

9.4 System TAP connection................................................................................................................................................195

9.4.1 IR Codes.......................................................................................................................................................195

9.5 JTAG status and control registers.................................................................................................................................196

9.5.1 MDM-AP Control Register..........................................................................................................................197

9.5.2 MDM-AP Status Register............................................................................................................................199

9.6 Debug Resets................................................................................................................................................................200

9.7 AHB-AP........................................................................................................................................................................201

9.8 ITM...............................................................................................................................................................................202

9.9 Core Trace Connectivity...............................................................................................................................................202

9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................202

9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................203

9.11.1 Performance Profiling with the ETB...........................................................................................................203

9.11.2 ETB Counter Control...................................................................................................................................204

9.12 TPIU..............................................................................................................................................................................204

9.13 DWT.............................................................................................................................................................................204

9.14 Debug in Low Power Modes........................................................................................................................................205

9.14.1 Debug Module State in Low Power Modes.................................................................................................206

9.15 Debug & Security.........................................................................................................................................................206

Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................207

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 9

Section Number Title Page

10.2 Signal Multiplexing Integration....................................................................................................................................207

10.2.1 Port control and interrupt module features..................................................................................................208

10.2.2 Clock gating.................................................................................................................................................208

10.2.3 Signal multiplexing constraints....................................................................................................................208

10.3 Pinout............................................................................................................................................................................209

10.3.1 K30 Signal Multiplexing and Pin Assignments...........................................................................................209

10.3.2 K30 Pinouts..................................................................................................................................................214

10.4 Module Signal Description Tables................................................................................................................................215

10.4.1 Core Modules...............................................................................................................................................215

10.4.2 System Modules...........................................................................................................................................216

10.4.3 Clock Modules.............................................................................................................................................217

10.4.4 Memories and Memory Interfaces...............................................................................................................217

10.4.5 Analog..........................................................................................................................................................218

10.4.6 Communication Interfaces...........................................................................................................................219

10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................222

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................225

11.1.1 Overview......................................................................................................................................................225

11.1.2 Features........................................................................................................................................................225

11.1.3 Modes of operation......................................................................................................................................226

11.2 External signal description............................................................................................................................................227

11.3 Detailed signal descriptions..........................................................................................................................................227

11.4 Memory map and register definition.............................................................................................................................227

11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................234

11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................236

11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................237

11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................237

11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................238

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

10 Freescale Semiconductor, Inc.

Dieses Handbuch passt für folgende Modelle

Inhaltsverzeichnis

Andere NXP Semiconductors Mikrocontroller Handbücher

NXP Semiconductors

NXP Semiconductors i.MX31 Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors MTRCKTSPS5744P Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors Freescale MC9S12XE Series Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors AN11844 Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors QN9080 Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors UM10574 Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors S32R27 Leitfaden

NXP Semiconductors

NXP Semiconductors PN7462 series Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors MPC5777M Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors SLN-LOCAL2-IOT Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors QN9020 mini DK Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors S12ZVMAEVB Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors ARM Cortex M0+ Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors freescale semiconductor CSM12D Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors Freescale Kinetis TWR-KV58F220M Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors Freescale Semiconductor MPC8569E-MDS-PB Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors freescale Kinetis TWR-KV10Z32 Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors AN11268 Fehlerbehebungshandbuch

NXP Semiconductors

NXP Semiconductors KE1xF Series Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors MRF300AN Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors LPC18xx series Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors MPC5566 Bedienungsanleitung

NXP Semiconductors

NXP Semiconductors Freescale DEMOEM MCF51EM Betriebsanleitung

NXP Semiconductors

NXP Semiconductors MPC5606BK Bedienungsanleitung

Beliebte Mikrocontroller Handbücher anderer Marken

AMS

AMS AS7261 Demo Kit Bedienungsanleitung

Novatek

Novatek NT6861 Bedienungsanleitung

Espressif Systems

Espressif Systems ESP8266 SDK Einrichtungshandbuch

Nuvoton

Nuvoton ISD61S00 ChipCorder Leitfaden

STMicrolectronics

STMicrolectronics ST7 Assembler Linker Bedienungsanleitung

Texas Instruments

Texas Instruments Chipcon CC2420DK Bedienungsanleitung

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM Bedienungsanleitung

NEC

NEC 78GK0S/K 1+ Series Montage- und Bedienungsanleitung

Mikroe

Mikroe SEMITECH N-PLC Click Montage- und Bedienungsanleitung

Intel

Intel Agilex Bedienungsanleitung

Cypress

Cypress CY4607 HX2VL Bedienungsanleitung

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE Bedienungsanleitung

Texas Instruments

Texas Instruments TMS320F2837 D Series Bedienungsanleitung

CYPRES

CYPRES CY14NVSRAMKIT-001 Bedienungsanleitung

Texas Instruments

Texas Instruments INA-DUAL-2AMP-EVM Bedienungsanleitung

Espressif Systems

Espressif Systems ESP8266EX Betriebsanleitung

Abov

Abov AC33M8128L Bedienungsanleitung

Laird

Laird BL654PA Bedienungsanleitung

NXP Semiconductors freescale K30 Series Bedienungsanleitung

Beliebte Mikrocontroller Handbücher anderer Marken