NXP Semiconductors LPC824M201JHI33 Bedienungsanleitung

UM10800

LPC82x User manual

Rev. 1.2 — 5 October 2016 User manual

Document information

Info Content

Keywords LPC82x, LPC824M201JHI33, LPC822M101JHI33, LPC824M201JDH20,

LPC822M101JDH20, LPC82x UM, LPC82x user manual, LPC820

Abstract LPC82x User manual

User manual Rev. 1.2 — 5 October 2016 2 of 487

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors UM10800

LPC82x User manual

Revision history

Rev Date Description

1.2 20161005 LPC82x User manual.

Modifications: •Updated Table 383 “Error codes”: added error codes 0x0006 0009 and 0x0006 000A.

•Added bits: 24 - ADC_RST_N; 29 - DMA_RST_N to Table 23 “Peripheral reset control register

(PRESETCTRL, address 0x4004 8004) bit description”.

•Added Section 12.5.7 “Channel chaining”.

1.1 20160524 LPC82x User manual.

Modifications: •Removed internal comments from Section 16.6.24 “SCT event enable registers 0 to 7”

•Changed main clock to system clock in the first paragraph in Section 26.5.1.1 “Param0: system PLL

input frequency and Param1: expected system clock”.

•Updated Section 25.6.2 “IAP commands”.

•Updated Table 308 “LPC82x flash configuration”: corrected the page numbers of sectors 21 - 31.

•Updated Section 16.6 “Register description” to fix the polarity for REGMODE.

–REGMODEn = 0: Registers operate as match and reload registers.

–REGMODEn = 1: Registers operate as capture and capture control registers.

•Changed signature generation start address (corresponds to AHB byte address bits[20:4]) to

signature generation start address (corresponds to AHB byte address bits[18:2]).

•Added a note to Table 236 “SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit

description” and Table 237 “SCT DMA 1 request register (DMAREQ1, address 0x5000 C060) bit

description”.

•Changed the ISP entry pin in Section 31.5.2 “Debug connections for SWD” to PIO0_20; was

PIO0_1.

•Added reserved blocks in Table 222 “Register overview: State Configurable Timer SCT/PWM (base

address 0x5000 4000)”: 0x220 to 0x2FF before EV0_STATE 0x340 to 0x4FF before OUT0_SET

1 20140918 Initial revision. LPC82x User manual.

User manual Rev. 1.2 — 5 October 2016 3 of 487

1.1 Introduction

The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and

8 KB of SRAM.

The peripheral complement of the LPC82x includes a CRC engine, four I2C-bus

interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer,

self-wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a

DMA, one 12-bit ADC and one analog comparator, function-configurable I/O ports through

a switch matrix, an input pattern match engine, and up to 29 general-purpose I/O pins.

Remark: For additional documentation, see Section 35.2 “References”.

1.2 Features

•System:

–ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to

30 MHz with single-cycle multiplier and fast single-cycle I/O port.

–ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

–System tick timer.

–AHB multilayer matrix.

–Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

–Micro Trace Buffer (MTB)

•Memory:

–Up to 32 KB on-chip flash programming memory with 64 Byte page write and

erase. Code Read Protection (CRP) supported.

–8 KB SRAM.

•ROM API support:

–bootloader.

–On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power

profiles) and integer divide.

–Flash In-Application Programming (IAP) and In-System Programming (ISP).

•Digital peripherals:

–High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to

32 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and glitch filter. GPIO direction

control supports independent set/clear/toggle of individual bits.

–High-current source output driver (20 mA) on four pins.

–High-current sink driver (20 mA) on two true open-drain pins.

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Chapter 1: LPC82x Introductory information

Rev. 1.2 — 5 October 2016 User manual

User manual Rev. 1.2 — 5 October 2016 4 of 487

NXP Semiconductors UM10800

Chapter 1: LPC82x Introductory information

–GPIO interrupt generation capability with boolean pattern-matching feature on

eight GPIO inputs.

–Switch matrix for flexible configuration of each I/O pin function.

–CRC engine.

–DMA with 18 channels and 9 trigger inputs.

•Timers:

–State Configurable Timer (SCTimer/PWM) with input and output functions

(including capture and match) for timing and PWM applications.

–Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

–Self-Wake-up Timer (WKT) clocked from either the IRC, a low-power,

low-frequency internal oscillator, or an external clock input in the always-on power

domain.

–Windowed Watchdog timer (WWDT).

•Analog peripherals:

–One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports

two independent conversion sequences.

–Comparator with four input pins and external or internal reference voltage.

•Serial peripherals:

–Three USART interfaces with pin functions assigned through the switch matrix and

one common fractional baud rate generator.

–Two SPI controllers with pin functions assigned through the switch matrix.

–Four I2C-bus interfaces. One I2C supports Fast-mode plus with 1 Mbit/s data rates

on two true open-drain pins and listen mode. Three I2Cs support data rates up to

400 kbit/s on standard digital pins.

•Clock generation:

–12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be

used as a system clock.

–Crystal oscillator with an operating range of 1 MHz to 25 MHz.

–Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

–PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock

input, or the internal RC oscillator.

–Clock output function with divider that can reflect all internal clock sources.

•Power control:

–Integrated PMU (Power Management Unit) to minimize power consumption.

–Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

–Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,

and I2C peripherals.

–Timer-controlled self-wake-up from Deep power-down mode.

–Power-On Reset (POR).

User manual Rev. 1.2 — 5 October 2016 5 of 487

NXP Semiconductors UM10800

Chapter 1: LPC82x Introductory information

–Brownout detect (BOD).

•Unique device serial number for identification.

•Single power supply (1.8 V to 3.6 V).

•Operating temperature range -40 °C to +105 °C.

•Available in a HVQFN33 (5x5) package.

1.3 Ordering options

1.4 General description

1.4.1 ARM Cortex-M0+ core configuration

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in

the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points.

The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO

access at address 0xA000 0000. The ARM Cortex M0+ core version is r0p1.

The core includes a single-cycle multiplier and a system tick timer (SysTick).

Table 1. Ordering information

Type number Package

Name Description Version

LPC824M201JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 5 5 0.85 mm n/a

LPC822M101JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 5 5 0.85 mm n/a

LPC824M201JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

LPC822M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

Table 2. Ordering options

Type number Flash/

KB SRAM/

KB USART I2CSPI ADC

channels Comparator GPIO Package

LPC824M201JHI33 32 8 3 4 2 12 Y 29 HVQFN33

LPC822M101JHI33 16 4 3 4 2 12 Y 29 HVQFN33

LPC824M201JDH20 32 8 3 4 2 5 Y 16 TSSOP20

LPC822M101JDH20 16 4 3 4 2 5 y 16 TSSOP20

User manual Rev. 1.2 — 5 October 2016 6 of 487

NXP Semiconductors UM10800

Chapter 1: LPC82x Introductory information

1.5 Block diagram

Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or

have DMA request lines.

Fig 1. LPC82x block diagram

SRAM

4/8 KB

ARM

CORTEX-M0+

TEST/DEBUG

INTERFACE

FLASH

16/32 KB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

RESET, CLKIN

clocks and

controls

LPC82xM

aaa-014399

slave

slave slave

ROM

slave

CRC

slave master

PIN INTERRUPTS/

PATTERN MATCH

AHB-LITE BUS

IRC

WDOsc

BOD

POR

SPI0/1

USART0/1/2

SDA

SCL

SCT_PIN[3:0]

29 x

PIO0

29 x

WWDT

IOCON

PMU

SELF

WAKE-UP TIMER

MULTI-RATE TIMER

I2C0/1/2/3

SCTIMER/

PWM

SWITCH

MATRIX

SCT_OUT[6:0]

COMPARATOR

XTALIN

XTALOUT

ACMP_O

SYSCON

RXD, CTS

TXD, RTS

ACMP_I[4:1]

VDDCMP

ADC

ADC_[11:0]

SCK, SSEL

MISO, MOSI

ALWAYS-ON POWER DOMAIN

XTAL

SCLK

CLKOUT

SWCLK, SWD

INPUT MUX

DMA

User manual Rev. 1.2 — 5 October 2016 7 of 487

2.1 How to read this chapter

The memory mapping is identical for all LPC82x parts. Different LPC82x parts support

different flash and SRAM memory sizes.

2.2 General description

The LPC82x incorporates several distinct memory regions. Figure 2 shows the overall

map of the entire address space from the user program viewpoint following reset.

The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals.

Each peripheral is allocated 16 KB of space simplifying the address decoding.

The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and

sleep mode control, are located on the private peripheral bus.

The GPIO port and pin interrupt/pattern match registers are accessed by the ARM

Cortex-M0+ single-cycle I/O enabled port (IOP).

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Chapter 2: LPC82x memory mapping

Rev. 1.2 — 5 October 2016 User manual

User manual Rev. 1.2 — 5 October 2016 8 of 487

NXP Semiconductors UM10800

Chapter 2: LPC82x memory mapping

2.2.1 Memory mapping

2.2.2 Micro Trace Buffer (MTB)

The LPC82x supports the ARM Cortex-M0+ Micro Trace Buffer. See Section 31.5.4.

The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.

Fig 2. LPC82x Memory mapping

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 0000

0x4005 8000

0x4005 C000

0x4006 0000

0x4006 4000

0x4006 8000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

MRT

reserved

12-bit ADC

self wake-up timer

reserved

WWDT

analog comparator

PMU

30 - 31 reserved

0x4002 C000

0x4003 0000

0x4003 4000

DMA TRIGMUX

input mux

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1FFF 0000

0x1FFF 3000

0x2000 0000

0x5000 0000

0x5000 4000

0xFFFF FFFF

reserved

0x4000 0000

0x4008 0000

APB peripherals

CRC

0x5000 8000

SCTimer/PWM

0x5000 C000

0xA000 0000

GPIO

0xA000 4000

0xA000 8000

GPIO PINT

0x1000 1000

4 KB SRAM0

0x1001 2000

4 KB SRAM1

0x1000 0000

LPC82x

0x0000 8000

32 KB on-chip flash

12 KB boot ROM

0x1400 0000

0x1400 1000

4 KB MTB registers

0x0000 0000

0x0000 00C0

active interrupt vectors

reserved

DMA

reserved

flash controller

SPI0

reserved

switch matrix

IOCON

system control (SYSCON)

19 reserved

0x4005 4000

20 I2C0

21 I2C1

23 SPI1

24 reserved

0x4006 C000

0x4007 0000

USART0

26 USART1

27 USART2

0x4007 4000

28 I2C2

0x4007 8000

29 I2C3

reserved

0xE000 0000

0xE010 0000

private peripheral bus

User manual Rev. 1.2 — 5 October 2016 9 of 487

3.1 How to read this chapter

The bootloader is identical for all parts.

3.2 Features

•12 KB on-chip boot ROM

•Contains the bootloader with In-System Programming (ISP) facility and the following

APIs:

–In-Application Programming (IAP) of flash memory

–Power profiles for optimizing power consumption and system performance

–USART driver

–ADC driver

–SPI driver

–I2C driver

–Integer divide routines

3.3 Basic configuration

The clock to the ROM is enabled by default. No configuration is required to use the ROM

APIs.

3.4 Pin description

When the ISP entry pin is pulled LOW on reset, the part enters ISP mode and the ISP

command handler starts up. In ISP mode, pin PIO0_0 is connected to function U0_RXD

and pin PIO0_4 is connected to function U0_TXD on the USART0 block.

3.5 General description

3.5.1 Bootloader

The bootloader controls initial operation after reset and also provides the means to

accomplish programming of the flash memory via USART. This could be initial

programming of a blank device, erasure and re-programming of a previously programmed

device, or programming of the flash memory by the application program in a running

system.

UM10800

Chapter 3: LPC82x Boot ROM

Rev. 1.2 — 5 October 2016 User manual

Table 3. Pin location in ISP mode

ISP entry pin USART RXD USART TXD

PIO0_12 PIO0_0 PIO0_4

User manual Rev. 1.2 — 5 October 2016 10 of 487

NXP Semiconductors UM10800

Chapter 3: LPC82x Boot ROM

The bootloader code is executed every time the part is powered on or reset. The

bootloader can execute the ISP command handler or the user application code. A LOW

level after reset at the ISP entry pin is considered as an external hardware request to start

the ISP command handler via USART.

For details on the boot process, see Section 3.6.2 “Boot process”.

Remark: SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and

the memory content in this area is retained during reset. SRAM memory is not retained

when the part powers down or enters Deep power-down mode.

Assuming that power supply pins are at their nominal levels when the rising edge on

RESET pin is generated, it may take up to 3 ms before the ISP entry pin is sampled and

the decision whether to continue with user code or ISP handler is made. The bootloader

performs the following steps (see Figure 4):

1. If the watchdog overflow flag is set, the bootloader checks whether a valid user code

is present. If the watchdog overflow flag is not set, the ISP entry pin is checked.

2. If there is no request for the ISP command handler execution (ISP entry pin is

sampled HIGH after reset), a search is made for a valid user program.

3. If a valid user program is found then the execution control is transferred to it. If a valid

user program is not found, the bootloader attempts to load a valid user program via

the USART interface.

Remark: The sampling of pin the ISP entry pin can be disabled through programming

flash location 0x0000 02FC (see Section 25.5.3 “Code Read Protection (CRP)”).

3.5.2 ROM-based APIs

Once the part has booted, the user can access several APIs located in the boot ROM to

access the flash memory, optimize power consumption, and operate the USART and I2C

peripherals.

The structure of the boot ROM APIs is shown in Figure 3.

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