ST EVALSP320SCPU Bedienungsanleitung

March 2012 Doc ID 022592 Rev 1 1/29

UM1499

User manual

EVALSP320SCPU evaluation board for SPEAr320S

Introduction

This document applies to revision 2.0 SPEAr320S CPU evaluation boards.

This board can be used to evaluate SPEAr320S microprocessors; the evaluation board kit

comprises one board, one serial cable interface, and one power supply.

CPU board features

■SPEAr320S embedded MPU

■Up to 2 Gbit DDR2 333 MHz (standard 128 Mbytes)

■Up to 16 Mbyte Serial Flash memory (standard 8 Mbytes)

■Two USB 2.0 full host port channels

■One USB 2.0 host device port

■One serial port (up to 115 baud)

■JTAG debug ports

Figure 1. EVALSP320SCPU evaluation board

Top Bottom

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Contents UM1499

2/29 Doc ID 022592 Rev 1

Contents

1 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Booting procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Dynamic memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Static memory subsystem (Serial Flash memory) . . . . . . . . . . . . . . . . . . . 7

2.3 USB 2.0 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Real time clock (battery powered) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.7 General power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.8 Reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Expansion connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Switch and jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Switch 1 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Switch 2 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 Jumpers and connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Board components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Appendix ALicense agreements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

UM1499 List of tables

Doc ID 022592 Rev 1 3/29

List of tables

Table 1. Switch SW1 bits [2:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. CPU board extension connector J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. CPU board extension connector J13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Switch 1 (SoC functional configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Switch 1 (debug configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. Switch 1 (functional configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Switch 2 settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. CPU board components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

List of figures UM1499

4/29 Doc ID 022592 Rev 1

List of figures

Figure 1. EVALSP320SCPU evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. EVALSP320SCPU board block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Serial cable setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. 86-pin connectors (J12 and J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. SPEAr320S CPU evaluation board layout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6. SPEAr320S CPU evaluation board layout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . 22

UM1499 Getting started

Doc ID 022592 Rev 1 5/29

1 Getting started

Warning: This board contains static sensitive devices.

The EVALSP320SCPU board is shipped in protective anti-static packaging. Do not submit

the board to high electrostatic potentials, and follow good practices for working with static

sensitive devices.

●Wear an anti-static wristband. Wearing a simple anti-static wristband can help

prevent ESD from damaging the board.

●Zero potential. Always touch a grounded conducting material before handling the

board, and periodically while handling it.

●Use an anti-static mat. When configuring the board, place it on and anti-static mat to

reduce the possibility of ESD damage.

●Handle only the edges. Handle the board by its edges only, and avoid touching board

components.

1.1 Connections

Refer to Figure 5 on page 21.

1. Connect a serial cable from connector J17 (serial link) to a host PC.

2. On the host PC running Windows or Linux, start the Terminal program.

3. Connect the +5 V voltage adapter (supplied in the EVALSP320SCPU package) to the

J11 power voltage connector on the CPU board.

4. Apply power to the board.

5. The Terminal program displays a sequence of boot messages followed by the Linux

console prompt.

For more information, refer to user manual UM0844 Getting started with Linux for SPEAr,

available at www.st.com/spear.

1.2 Booting procedure

The SPEAr320S CPU evaluation board can boot a Linux kernel that has been pre-installed

in the serial NOR Flash.

At power on, the serial port outputs a brief header message with some uBoot information

(uBoot version, SDK version, and some internal hardware information). At this point you can

choose to:

●Stop the system directly in uBoot: Press the spacebar on the host computer

keyboard before the boot delay time expires (default is 3 seconds).

●Boot Linux: The system logs you in automatically as super user, and displays the

Linux shell prompt on the screen.

Functional description UM1499

6/29 Doc ID 022592 Rev 1

2 Functional description

The following figure shows the block diagram of the EVALSP320SCPU board.

Figure 2. EVALSP320SCPU board block diagram

2.1 Dynamic memory subsystem

The Dynamic memory subsystem comprises three major parts:

Memory chip

The SPEAr320S MPU supports up to 256 Mbytes of memory. Place and route is provided

for 2 chips but only one has been populated. The memory used is a Micron DDR2 device, its

part number is MT47H64M16HR-3 and its size is 128 Mbits x 8 (16 Mbits x 8 x 8 banks).

Local power supply

The local power supply is based on a monolithic voltage regulator for the chip set and

DDR2/3 (PM6641). It is generated locally in order to minimize the layout impact and also to

avoid any noise injection between different subsystems.

Expansion connector bottom side

NOR Flash DDR2

Power supply

Debug I/F

Serial I/F

USB 2.0

Host 1

USB 2.0

Host 2

USB 2.0

Device

SPEAr320S

UM1499 Functional description

Doc ID 022592 Rev 1 7/29

Signal termination

A parallel termination is added on the clock lines to compensate, if needed, for the layout

dissymmetry. Two 100k ohm resistors are used for each line in order to obtain an impedance

of 50 ohms. All the other terminations are directly inside the pads (both on the SPEAr320S

MPU and the memory sides).

2.2 Static memory subsystem (Serial Flash memory)

The SPEAr320S MPU supports up to 16 Mbytes of Serial Flash memory. Place and route

for 2 blocks of 8 Mbytes are provided on the board, but only one is populated. It is based on

an M25P64-VMF6P (Numonix) Serial Flash memory device.

Resistor R8 protects the Flash memory from any unwanted write access.

2.3 USB 2.0 subsystem

Host ports

The board has two host ports that are fully compliant with the USB 2.0 specification (two

controllers with one port each). This means that the two hosts can work in concurrent mode

with the maximum possible bandwidth. Each host has also full control of the VBUS supplied

by the ST2052 power switch that also provides over current protection in case of a short

circuit in the USB cable.

Device port

The board has one USB 2.0 device port.

2.4 Debug interface

The JTAG interface can be used for static debugging, which means that it is possible to set a

breakpoint, and when the system stops, verify the contents of the memory or registers, or

both, and modify them if needed.

To select the debug feature, set Switch SW1 bits [2:1].

For more information on the ETM interface, refer to the trace box manufacturer’s

documentation (www.lauterbach.com, www.agilent.com, www.yokogawa.com).

Table 1. Switch SW1 bits [2:1]

Bit 2 Bit 1 Description

0 0 No debug features available

0 1 The ARM JTAG is connected to J4

Functional description UM1499

8/29 Doc ID 022592 Rev 1

2.5 Serial interface

One serial interface port is available. Typically used as an OS monitor, this port is available

on the J17 connector. It is possible to simulate a cross cable by changing the position of the

J22 jumpers.

Figure 3. Serial cable setting

2.6 Real time clock (battery powered)

The real time clock (RTC) is powered by an external battery (3V) in order to prevent data

loss even if the main power supply is switched off.

2.7 General power supply

From a 5 V external AC/DC regulator power source, this block generates all the required

voltages as follows:

●1.2V (Switching regulator PM6641) to supply the internal logic of the SPEAr320S MPU

●1.8V (Switching regulator PM6641) for the DDR2 memory

●2.5V (LDO regulator) for the analog portion of SPEAr320S

●3.3V (Switching regulator PM6641) to supply the other interfaces

A power monitor is also present to provide the general reset of the board.

2.8 Reset button

A manual reset button (P1) on the top of the board (see Figure 5 on page 21) resets the

microprocessor on the core board.

Nul

Modem

Cable

J22

Cross

Cable

J22

UM1499 Expansion connectors

Doc ID 022592 Rev 1 9/29

3 Expansion connectors

The CPU board has two 86-pin connectors (J12 and J13) that are used to extend the board.

On the board the connectors are horizontally center-aligned, and the distance between the

mechanical holes is 3400.00 th.

Tabl e 2 lists connector J12 pins.

Tabl e 3 on page 11 lists connector J13 pins.

Note: Connector through hole pins (10 pins) are connected to GND

Figure 4. 86-pin connectors (J12 and J13)

Table 2. CPU board extension connector J12

Pin Description Pin Description

1 +1.8V 2 +5V

3 +1.8V 4 +5V

5 +1.8V 6 +5V

7 +1.8V 8 +5V

9 PL_GPIO2 (RS232-TX LVTTL)(1) 10 PL_GPIO44

11 PL_GPIO3 (RS232-RX LVTTL)(2) 12 PL_GPIO39

13 RS232-TX(3) 14 PL_GPIO40

15 RS232-RX(4) 16 PL_GPIO38

17 PL_GPIO42 18 PL_GPIO29

19 PL_GPIO43 20 PL_GPIO37

21 PL_GPIO34 22 PL_GPIO30

23 PL_GPIO33 24 PL_GPIO28

25 PL_GPIO16 26 PL_GPIO26

27 PL_GPIO24 28 PL_GPIO27

29 PL_GPIO20 30 PL_GPIO9

31 PL_GPIO23 32 PL_GPIO13

33 PL_GPIO18 34 PL_GPIO8

Expansion connectors UM1499

10/29 Doc ID 022592 Rev 1

35 PL_GPIO11 36 PL_GPIO6

37 PL_GPIO19 38 PL_GPIO4

39 PL_GPIO15 40 PL_GPIO5

41 PL_GPIO14 42 NC

43 PL_GPIO36 44 NC

45 PL_GPIO41 46 NC

47 PL_GPIO35 48 NC

49 PL_GPIO31 50 +2.5V

51 PL_GPIO32 52 +2.5V

53 PL_GPIO25 54 +2.5V

55 PL_GPIO22 56 +2.5V

57 PL_GPIO21 58 INRESET

59 PL_GPIO17 60 nRESET

61 PL_GPIO12 62 +1.2V

63 PL_GPIO10 64 +1.2V

65 PL_GPIO7 66 +1.2V

67 PL_GPIO1 68 +1.2V

69 PL_GPIO0 70 +3.3V

71 NC 72 +3.3V

73 NC 74 +3.3V

75 NC 76 +3.3V

GND(5)

79 80

81 82

83 84

85 86

1. If J20 Jumper is set to pin2-3, otherwise NC.

2. If J21 Jumper is set to pin2-3, otherwise NC.

3. If J22 Jumper is set to pin2-4 and pin1-3, otherwise RS232-RX.

4. If J22 Jumper is set to pin2-4 and pin1-3, otherwise RS232-TX.

5. Physically connected to the internal metal plane of the connector. Pins 77 through 81 and 82 through 86

are shorted together.

Table 2. CPU board extension connector J12 (continued)

Pin Description Pin Description

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