Texas Instruments Sitara AM1335 Series Bedienungsanleitung

Sitara™ AM335x ARM®Cortex™-A8

Microprocessors (MPUs)

Silicon Revisions 2.1, 2.0, 1.0

Silicon Errata

Literature Number: SPRZ360F

October 2011–Revised November 2013

Contents

1 Introduction ........................................................................................................................ 3

1.1 AM335x Device and Development Support Tool Nomenclature .................................................. 3

1.2 Revision Identification ................................................................................................... 4

2 All Errata Listed With Silicon Revision Number ...................................................................... 6

3 Usage Notes and Known Design Exceptions to Functional Specifications ................................. 8

3.1 Usage Notes ............................................................................................................. 8

3.1.1 LCD: Color Assignments of LCD_DATA Terminals ..................................................... 8

3.1.2 DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit ............................ 8

3.1.3 Boot: USB Boot ROM Code Uses Default DATAPOLARITY .......................................... 9

3.1.4 Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV Cause NAND Boot

Issue ........................................................................................................... 9

3.1.5 Pin Multiplexing: Valid IO Sets and Restrictions ....................................................... 10

3.1.6 Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue ........... 10

3.1.7 OSC1: RTC_XTALIN Terminal Has an Internal Pull-up Resistor When OSC1 is Disabled ...... 11

3.2 Known Design Exceptions to Functional Specifications .......................................................... 12

Revision History ......................................................................................................................... 38

2Table of Contents SPRZ360F–October 2011–Revised November 2013

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Silicon Errata

SPRZ360F–October 2011–Revised November 2013

Sitara™ AM335x ARM®Cortex™-A8

Microprocessors (MPUs)

(Silicon Revision 2.1, 2.0, 1.0)

1 Introduction

This document describes the known exceptions to the functional specifications for the Sitara™ AM335x

ARM®Cortex™-A8 Microprocessors (MPUs). [See the Sitara AM335x ARM Cortex-A8 Microprocessors

(MPUs) data manual (literature number SPRS717).]

For additional information, see the latest version of the Sitara AM335x ARM Cortex-A8 Microprocessors

(MPUs) Technical Reference Manual (literature number SPRUH73).

1.1 AM335x Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)

(for example, XAM3358ZCE). Texas Instruments recommends two of three possible prefix designators for

its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development

from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

X — Experimental device that is not necessarily representative of the final device's electrical

specifications and may not use production assembly flow.

P — Prototype device that is not necessarily the final silicon die and may not necessarily meet final

electrical specifications.

null — Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX — Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS — Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

Sitara is a trademark of Texas Instruments.

Cortex is a trademark of ARM Ltd or its subsidiaries.

ARM is a registered trademark of ARM Ltd or its subsidiaries.

All other trademarks are the property of their respective owners.

SPRZ360F–October 2011–Revised November 2013 Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0)

Lot Trace Code

XAM3352AZCE

YMLLLLS

962 ZCE

Device Revision Lot Trace Code

XAM3359AZCZ

YMLLLLS

962 ZCZ

Device Revision

Introduction

www.ti.com

1.2 Revision Identification

The device revision can be determined by the symbols marked on the top of the package. Figure 1

provides an example of the AM335x device markings.

Figure 1. Example of Device Revision Codes for the AM335x Microprocessor

NOTES:

(A) Non-qualified devices are marked with the letters "X" or "P" at the beginning of the device name, while

qualified devices have a "blank" at the beginning of the device name.

(B) The AM3352 and AM3359 devices shown in this device marking example are two of several valid part

numbers for the AM335x family of devices.

(D) YM denotes year and month.

(E) LLLL denotes Lot Trace Code.

(F) 962 is a generic family marking ID.

(G) G1 denotes green, lead-free.

(H) ZCE or ZCZ is the package designator.

(I) S denotes Assembly Site Code.

(J) On some "X" devices, the device speed may not be shown.

4SPRZ360F–October 2011–Revised November 2013

Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0) Submit Documentation Feedback

www.ti.com

Introduction

Silicon revision is identified by a code marked on the package. The code is of the format AM3352x or

AM3358x, where "x" denotes the silicon revision. Table 1 lists the information associated with each silicon

revision for each device type. For more details on device nomenclature, see the device-specific data

manual.

Table 1. Production Device Revision Codes

DEVICE REVISION CODE SILICON REVISION COMMENTS

(blank) 1.0 Silicon revision is new

A 2.0 Silicon revision 2.0

B 2.1 Silicon revision 2.1

Each silicon revision uses a specific revision of TI's ARM®Cortex™-A8 processor. The ARM Cortex-A8

processor variant and revision can be read from the Main ID Register. The DEVREV field (bits 31-28) of

the Device_ID register located at address 0x44E10600 provides a 4-bit binary value that represents the

device revision. The ROM code revision can be read from address 2BFFCh. The ROM code version

consists of two decimal numbers: major and minor. The major number is always 22, minor number counts

ROM code version. The ROM code version is coded as hexadecimal readable values; for example, ROM

version 22.02 is coded as 0000 2202h. Table 2 shows the ARM Cortex-A8 Variant and Revision, Device

Revision, and ROM Code Revision values for each silicon revision of the device.

Table 2. Silicon Revision Variables

SILICON ARM CORTEX-A8 DEVICE ROM

REVISION VARIANT AND REVISION REVISION REVISION

1.0 r3p2 0000 22.02

2.0 r3p2 0001 22.03

2.1 r3p2 0010 22.03

SPRZ360F–October 2011–Revised November 2013 Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0)

All Errata Listed With Silicon Revision Number

www.ti.com

2 All Errata Listed With Silicon Revision Number

Advisories are numbered in the order in which they were added to this document. Some advisory numbers

may be moved to the next revision and others may have been removed because the design exception

was fixed or documented in the device-specific data manual or peripheral user's guide. When items are

moved or deleted, the remaining numbers remain the same and are not re-sequenced.

Table 3. All Usage Notes

SILICON REVISION AFFECTED

NUMBER TITLE 1.0 2.0 2.1

Section 3.1.1 LCD: Color Assignments of LCD_DATA Terminals X X X

DDR3: JEDEC Compliance for Maximum Self-Refresh

Section 3.1.2 XXX

Command Limit

Section 3.1.3 Boot: USB Boot ROM Code Uses Default DATAPOLARITY X X X

Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and

Section 3.1.4 X

RMII2_CRS_DV Cause NAND Boot Issue

Section 3.1.5 Pin Multiplexing: Valid IO Sets and Restrictions X X X

Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS

Section 3.1.6 X X

Cause NAND Boot Issue

OSC1: RTC_XTALIN Terminal Has an Internal Pull-up

Section 3.1.7 XXX

Resistor When OSC1 is Disabled

Table 4. All Design Exceptions to Functional Specifications

SILICON REVISION AFFECTED

NUMBER TITLE 1.0 2.0 2.1

DDR2, DDR3, mDDR PHY: Control and Status Registers

Advisory 1.0.1 XXX

Configured for Write Only

Debug Subsystem: EMU[4:2] Signals Are Not Available by

Advisory 1.0.2 XXX

Default After Reset

Debug Subsystem: Internal Inputs Tied-off to the Wrong

Advisory 1.0.3 XXX

Value

Advisory 1.0.4 PRU-ICSS: Clock Domain Crossing (CDC) Issue X

Advisory 1.0.5 RTC: 32.768-kHZ Clock is Gating Off X

EXTINTn: Input Function of the EXTINTn Terminal is

Advisory 1.0.6 X

Inverted

Advisory 1.0.7 Boot: Ethernet Boot ROM Code PHY Link Speed Detection X

Boot: Ethernet Boot ROM Code Sends an Incorrect Vendor

Advisory 1.0.8 X

Class Identifier in BOOTP Packet

Ethernet Media Access Controller and Switch Subsystem:

Advisory 1.0.9 C0_TX_PEND and C0_RX_PEND Interrupts Not Connected X

to ARM Cortex-A8

GMII_SEL Register: RGMII1_IDMODE and

Advisory 1.0.10 RGMII2_IDMODE Bits Reset to Non-supported Mode of X

Operation

USB: Attached Non-compliant USB Device that Responds

Advisory 1.0.11 X

to Spurious Invalid Short Packet May Lock Up Bus

UART: Extra Assertion of FIFO Transmit DMA Request,

Advisory 1.0.12 XXX

UARTi_DMA_TX

USB: Data May be Lost When USB Subsystem is Operating

Advisory 1.0.13 in DMA Mode and More Than One Endpoint is Transferring X

Data

GMII_SEL and CPSW Related Pad Control Registers:

Advisory 1.0.14 Context of These Registers is Lost During Transitions of X

PD_PER

ARM Cortex-A8: OPP50 Operation on MPU Domain Not

Advisory 1.0.15 X

Supported

6SPRZ360F–October 2011–Revised November 2013

Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon Revision

2.1, 2.0, 1.0) Submit Documentation Feedback

www.ti.com

All Errata Listed With Silicon Revision Number

Table 4. All Design Exceptions to Functional Specifications (continued)

SILICON REVISION AFFECTED

NUMBER TITLE 1.0 2.0 2.1

RMII: 50-MHz RMII Reference Clock Output Does Not

Advisory 1.0.16 XXX

Satisfy Clock Input Requirements of RMII Ethernet PHYs

Advisory 1.0.17 VDDS_DDR: High-Power Consumption During DeepSleep0 X

ROM: Ethernet Boot Code Does Not Change Default

Advisory 1.0.18 Direction of RMII1 Reference Clock When Booting from X

Ethernet Using RMII

DDR3: Fully-Automated Hardware READ and WRITE

Advisory 1.0.19 XXX

Leveling Not Supported

Boot: USB Boot ROM Code Overlapping Data in TXFIFO

Advisory 1.0.20 X

and RXFIFO

SmartReflex: Limited Support Due to Issue Described in

Advisory 1.0.21 X

Advisory 1.0.15

EMIF: Dynamic Voltage Frequency Scaling (DVFS) is Not

Advisory 1.0.22 XXX

Supported

Ethernet Media Access Controller and Switch Subsystem:

Advisory 1.0.23 XXX

Reset Isolation Feature is Not Supported

Boot: System Boot is Not Reliable if Reset is Asserted

Advisory 1.0.24 XXX

While Operating in OPP50

Boot: System Boot Temporarily Stalls if an Attempt to Boot

Advisory 1.0.25 XXX

from Ethernet is Not Successful

Advisory 1.0.26 I2C: SDA and SCL Open-Drain Output Buffer Issue X X

Advisory 1.0.27 LCDC: LIDD DMA Mode Issue X X X

LCDC: Raster Mode, Hardware Auto Underflow Restart

Advisory 1.0.28 XXX

Does Not Work

Latch-up Performance: Latch-up Performance Limits for

Advisory 1.0.29 X X

Silicon Revsions 1.0 and 2.0

OSC0 and OSC1: Noise Immunity Improved When Crystal

Advisory 1.0.30 XXX

Circuit is Connected Directly to PCB Digital Ground

Advisory 1.0.31 TSC_ADC: False Pen-up Interrupts X X X

TSC_ADC: Terminals May be Temporarily Connected

Advisory 1.0.32 Together Through Internal Paths During Power-up X X X

Sequence

USB Host: USB Low-Speed Receive-to-Transmit Inter-

Advisory 1.0.33 XXX

Packet Delay

USB2PHY: Register Accesses After a USB Subsystem Soft

Advisory 1.0.34 XXX

Reset May Lock Up the Entire System

UART: Transactions to MDR1 Register May Cause

Advisory 1.0.35 XXX

Undesired Effect on UART Operation

EMU0 and EMU1: Terminals Must Be Pulled High Before

Advisory 1.0.36 XXX

ICEPick Samples

SPRZ360F–October 2011–Revised November 2013 Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

PIXEL_n

000 0 0000R[7:3] G[7:2] B[7:3]

16-bit panel

24-bit panel

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

PIXEL_n

B[0] G[0] R[0] B[1] G[1] R[1] B[2] R[2] B[7:3] G[7:2] R[7:3]

16-bit panel

24-bit panel

Usage Notes and Known Design Exceptions to Functional Specifications

www.ti.com

3 Usage Notes and Known Design Exceptions to Functional Specifications

3.1 Usage Notes

This document contains Usage Notes. Usage Notes highlight and describe particular situations where the

device's behavior may not match presumed or documented behavior. This may include behaviors that

affect device performance or functional correctness. These notes may be incorporated into future

documentation updates for the device (such as the device-specific data manual), and the behaviors they

describe may or may not be altered in future device revisions.

3.1.1 LCD: Color Assignments of LCD_DATA Terminals

The blue and red color assignments to the LCD data pins are reversed when operating in RGB888

(24bpp) mode compared to RGB565 (16bpp) mode. In order to correctly display RGB888 data from the

SGX, or any source formatted as RGB in memory, it is necessary to connect the LCD panel as shown in

Figure 2. Using the LCD Controller with this connection scheme limits the use of RGB565 mode. Any data

generated for the RGB565 mode requires the red and blue color data values be swapped in order to

display the correct color.

Figure 2. RGB888 Mode LCD Controller Output Pin Mapping (LCD_DATA[23:0])

When operating the LCD Controller in RGB565 mode the LCD panel should be connected as shown in

Figure 3. Using the LCD Controller with this connection scheme limits the use of RGB888 mode. Any data

generated for the RGB888 mode requires the red and blue color data values be swapped in order to

display the correct color.

Figure 3. RGB565 Mode LCD Controller Output Pin Mapping (LCD_DATA[23:0])

3.1.2 DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit

When using DDR3 EMIF Self-Refresh, it is possible to violate the maximum refresh command requirement

specified in the JEDEC standard DDR3 SDRAM Specification (JESD79-3E, July 2010). This requirement

states that the DDR3 EMIF controller should issue no more than 16 refresh commands within any 15.6-μs

interval.

To avoid this requirement violation, when using the DDR3 EMIF and Self-Refresh (setting LP_MODE =

0x2 field in the PMCR), the SR_TIM value in the PMCR must to be programmed to a value greater than or

equal to 0x9.

8SPRZ360F–October 2011–Revised November 2013

Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0) Submit Documentation Feedback

www.ti.com

Usage Notes and Known Design Exceptions to Functional Specifications

3.1.3 Boot: USB Boot ROM Code Uses Default DATAPOLARITY

The AM335x USB PHYs supports a DATAPOLARITY feature that allows the data plus (DP) and data

minus (DM) data signals to be swapped. This feature was added to simplify PCB layout.

In some cases, the DP and DM data signals may need to cross over each other to connect to the

respective USB connector pins. Crossing these signals on the PCB may cause signal integrity issues if not

implemented properly since they must be routed as high-speed differential transmission lines. The

DATAPOLARITY feature in the USB PHYs can be used resolve this issue.

The DATAPOLARITY feature is controlled by DATAPOLARITY_INV (bit 23) of the respective USB_CTRL

The USB boot ROM code uses the default value for DATAPOLARITY_INV when booting from USB.

Therefore, the PCB must be designed to use the default DATAPOLARITY if the system must support USB

boot.

3.1.4 Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV Cause NAND Boot

Issue

The AM335x device multiplexes the GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV signals on the

same terminal. This causes a problem when the system must support NAND boot while an MII or RMII

Ethernet PHY is connected to port 2 of the Ethernet media access controller and switch (CPSW). The

GPMC_WAIT0 signal is required for NAND boot. The GMII2_CRS or RMII2_CRS_DV signal is required by

the respective MII or RMII Ethernet PHY and the only pin multiplexing option for these signals is

GPMC_WAIT0.

In this case, there are two sources that need to be connected to the GPMC_WAIT0 terminal. The NAND

READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS or

RMII CRS_DV output must source the GPMC_WAIT0 terminal when the application software is using port

2 of the CPSW. Therefore, a GPIO-controlled external 2-to-1 multiplexer must be implemented in the

system to select between the two sources. The GPIO selected to control the 2-to-1 multiplexer needs to

have an internal or external resistor that selects the NAND READY or BUSY output as soon as power is

applied and remains in that state until the application software initializes the CPSW.

The TI TS5A3157 SPDT analog switch is an example device that can be used as a 2-to-1 multiplexer.

This device inserts minimum propagation delay to the signal path since it is an analog switch. The

propagation delay inserted by the 2-to-1 multiplexer must be analyzed to confirm it does not cause timing

violations for the respective interface.

The NAND, Ethernet PHY, AM335x VDDSHV1, AM335x VDDSHV3 (when using the ZCZ package), and

2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share

common signals.

SPRZ360F–October 2011–Revised November 2013 Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0)

Usage Notes and Known Design Exceptions to Functional Specifications

www.ti.com

3.1.5 Pin Multiplexing: Valid IO Sets and Restrictions

The AM335x device contains many peripheral interfaces. In order to reduce package size and lower

overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex

up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,

only a certain number of sets, called IO Sets, are valid due to timing limitations. These valid IO Sets were

carefully chosen to provide many possible application scenarios for the user.

Texas Instruments has developed a Windows®-based application called Pin Mux Utility that helps a

system designer select the appropriate pin-multiplexing configuration for their AM335x-based product

design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to

ensure the pin multiplexing configuration selected for a design only uses valid IO Sets supported by the

AM335x device.

A few IO Sets have additional restrictions not defined in the Pin Mux Utility. These additional restrictions

are described below:

• MMC0, MMC1, MMC2 Interfaces

– Only Standard (STD) and High Speed (HS) modes are supported. SDR12, SDR25, SDR50 modes

as defined in SD3.0 specification are not supported.

• GEMAC_CPSW Interface

– Operation of GEMAC_CPSW is not supported for OPP50.

3.1.6 Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue

The AM335x device multiplexes the GPMC_WAIT0 and GMII2_CRS signals on the same terminal. This

causes a problem when the system must support NAND boot while an MII Ethernet PHY is connected to

port 2 of the Ethernet media access controller and switch (CPSW). The GPMC_WAIT0 signal is required

for NAND boot. The GMII2_CRS signal is required by the MII Ethernet PHY and the only pin multiplexing

option for these signals is GPMC_WAIT0.

In this case, there are two sources that need to be connected to the GPMC_WAIT0 terminal. The NAND

READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS

output must source the GPMC_WAIT0 terminal when the application software is using port 2 of the

CPSW. Therefore, a GPIO-controlled external 2-to-1 multiplexer must be implemented in the system to

select between the two sources. The GPIO selected to control the 2-to-1 multiplexer needs to have an

internal or external resistor that selects the NAND READY or BUSY output as soon as power is applied

and remains in that state until the application software initializes the CPSW.

The TI TS5A3157 SPDT analog switch is an example device that can be used as a 2-to-1 multiplexer.

This device inserts minimum propagation delay to the signal path since it is an analog switch. The

propagation delay inserted by the 2-to-1 multiplexer must be analyzed to confirm it does not cause timing

violations for the respective interface.

The NAND, Ethernet PHY, AM335x VDDSHV1, AM335x VDDSHV3 (when using the ZCZ package), and

2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share

common signals.

10 SPRZ360F–October 2011–Revised November 2013

Sitara™ AM335x ARM®Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0) Submit Documentation Feedback

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