Texas Instruments ADS1282 Bedienungsanleitung

4th-Order

Modulator

Programmable

Digital Filter

SPI

Interface

Calibration

Control

CLK

AVDD

AVSS

DVDD

DGND

Over-Range

Modulator Output

ADS1282

DOUT

DIN

DRDY

SCLK

SYNC

RESET

PWDN

PGA

MUX

Input 1

Input 2

VREFN VREFP

VCOM

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ADS1282

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

ADS1282 High-Resolution Analog-To-Digital Converter

1 Features 3 Description

The ADS1282 is an extremely high-performance,

1• High Resolution: single-chip analog-to-digital converter (ADC) with an

130-dB SNR (250 SPS) integrated, low-noise programmable gain amplifier

• High Accuracy: (PGA) and two-channel input multiplexer (mux). The

THD: –122 dB ADS1282 is suitable for the demanding needs of

INL: 0.5 ppm energy exploration and seismic monitoring

environments.

• Low-Noise PGA

• Two-Channel Input Mux The converter uses a fourth-order, inherently stable,

delta-sigma (ΔΣ) modulator that provides outstanding

• Inherently-Stable Modulator with Fast Responding noise and linearity performance. The modulator is

Overrange Detection used either in conjunction with the on-chip digital

• Flexible Digital Filter: filter, or can be bypassed for use with post

Sinc + FIR + IIR (Selectable) processing filters.

Linear or Minimum Phase Response The flexible input MUX provides an additional

Programmable High-Pass Filter external input for measurement, as well as internal

Selectable FIR Data Rates: 250 SPS to 4 kSPS self-test connections. The PGA features outstanding

• Filter Bypass Option low noise (5 nV/√Hz) and high input impedance,

• Low Power Consumption: 25 mW allowing easy interfacing to geophones and

hydrophones over a wide range of gains.

Shutdown: 10 μW

• Offset and Gain Calibration Engine The digital filter provides selectable data rates from

250 to 4000 samples per second (SPS). The high-

• SYNC Input pass filter (HPF) features an adjustable corner

• Analog Supply: frequency. On-chip gain and offset scaling registers

Unipolar (+5 V) or Bipolar (±2.5 V) support system calibration.

• Digital Supply: 1.8 V to 3.3 V The synchronization input (SYNC) can be used to

synchronize the conversions of multiple ADS1282s.

2 Applications The SYNC input also accepts a clock input for

• Energy Exploration continuous alignment of conversions from an external

source.

• Seismic Monitoring

• High-Accuracy Instrumentation Together, the amplifier, modulator, and filter dissipate

25 mW. The ADS1282 is available in a compact

TSSOP-28 package and is fully specified from –40°C

to +85°C, with a maximum operating range to

+125°C.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS1282

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

4 Ordering Information

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or visit the device product folder at ti.com.

5 Specifications

5.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted).

ADS1282, ADS1282H UNIT

AVDD to AVSS –0.3 to +5.5 V

AVSS to DGND –2.8 to +0.3 V

DVDD to DGND –0.3 to +3.9 V

Input current 100, momentary mA

Input current 10, continuous mA

Analog input voltage AVSS – 0.3 to AVDD + 0.3 V

Digital input voltage to DGND –0.3 to DVDD + 0.3 V

Maximum junction temperature +150 °C

Operating temperature range –40 to +125 °C

Storage temperature range –60 to +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

Product Folder Links: ADS1282

ADS1282

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SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

5.2 Electrical Characteristics

Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz,

VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, and fDATA = 1000SPS, unless otherwise

noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale input voltage VIN = (AINP – AINN) ±VREF/(2 × PGA) V

Absolute input range AINP or AINN AVSS + 0.7 AVDD – 1.25 V

PGA input voltage noise density 5 nV/√Hz

Chop on 1 GΩ

Differential input impedance Chop off 100 GΩ

Common-mode input impedance 100 MΩ

Input bias current 1 nA

Crosstalk f = 31.25Hz –135 dB

MUX on-resistance 30 Ω

PGA OUTPUT (CAPP, CAPN)

Absolute output range AVSS + 0.4 AVDD – 0.4 V

PGA differential output impedance 600 Ω

Output impedance tolerance ±10%

External bypass capacitance 10 100 nF

Modulator differential input impedance 55 kΩ

AC PERFORMANCE

Signal-to-noise ratio(2) SNR 120 124 dB

PGA = 1...16 –122 –114

Total harmonic distortion(3) THD PGA = 32 –117 –110 dB

PGA = 64 –115

Spurious-free dynamic dB

SFDR 123

range

DC PERFORMANCE

Resolution No missing codes 31 Bits

FIR filter mode 250 4000 SPS

Data rate fDATA Sinc filter mode 8000 128,000 SPS

Integral nonlinearity (INL)(4) Differential input 0.00005 0.0004 % FSR(5)

Offset error 50 200 μV

Offset error after calibration(6) Shorted input 1 μV

Offset drift 0.02 μV/°C

Gain error(7) –1.5% –1.0% –0.5%

Gain error after calibration(6) 0.0002%

PGA = 1 2 ppm/°C

Gain drift PGA = 16 9 ppm/°C

Gain matching(8) 0.3% 0.8%

Common-mode rejection fCM = 60Hz(9) 95 110 dB

AVDD, AVSS 80 90

Power-supply rejection fPS = 60Hz(9) dB

DVDD 90 115

(1) fCLK = system clock.

(2) VIN = 20mVDC/PGA; see Table 1.

(3) VIN = 31.25Hz, –0.5dBFS.

(4) Best-fit method.

(5) FSR: Full-scale range = ±VREF/(2 × PGA).

(6) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).

(7) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.

(8) Gain match relative to PGA = 1.

(9) fCM is the input common-mode frequency. fPS is the power-supply frequency.

Product Folder Links: ADS1282

ADS1282

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

www.ti.com

Electrical Characteristics (continued)

Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz,

VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, and fDATA = 1000SPS, unless otherwise

noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOLTAGE REFERENCE INPUTS

(AVDD – AVSS)

Reference input voltage (VREF = VREFP – VREFN) 0.5 5 V

+ 0.2

Negative reference input VREFN AVSS – 0.1 VREFP – 0.5 V

Positive reference input VREFP VREFN + 0.5 AVDD + 0.1 V

Reference input impedance 85 kΩ

DIGITAL FILTER RESPONSE

Passband ripple ±0.003 dB

Passband (–0.01dB) 0.375 × fDATA Hz

Bandwidth (–3dB) 0.413 × fDATA Hz

High-pass filter corner 0.1 10 Hz

Stop band attenuation(10) 135 dB

Stop band 0.500 × fDATA Hz

Minimum phase filter(11) 5/fDATA

Group delay s

Linear phase filter 31/fDATA

Minimum phase filter 62/fDATA

Settling time (latency) s

Linear phase filter 62/fDATA

DIGITAL INPUT/OUTPUT

VIH 0.8 × DVDD DVDD V

VIL DGND 0.2 × DVDD V

VOH IOH = 1mA 0.8 × DVDD V

VOL IOL = 1mA 0.2 × DVDD V

Input leakage 0 < VDIGITAL IN < DVDD ±10 μA

Clock input fCLK 1 4.096 MHz

Serial clock rate fSCLK fCLK/2 MHz

POWER SUPPLY

AVSS –2.6 0 V

AVDD AVSS + 4.75 AVSS + 5.25 V

DVDD 1.65 3.6 V

Normal operation 4.5 6.5 |mA|

AVDD, AVSS current Standby mode 1 15 |μA|

Power-down mode 1 15 |μA|

Normal operation 0.6 0.8 mA

Modulator mode 0.1 mA

DVDD current Standby mode 25 50 μA

Power-down mode(12) 1 15 μA

Normal operation 25 35 mW

Power dissipation Standby mode 90 250 μW

Power-down mode 10 125 μW

(10) Input frequencies in the range of NfCLK/512 ± fDATA/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency

ranges intermodulation = 120dB, typ.

(11) At dc; see Figure 44.

(12) CLK input stopped.

Product Folder Links: ADS1282

SCLK

DIN

DOUT

tSCLK tSPWH

tSCDL

tDIST

tDIHD

tSPWL

tSCDL

tDOHD

tDOPD

ADS1282

www.ti.com

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

6 Timing Diagram

6.1 Timing Requirements

At TA= –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted.

PARAMETER DESCRIPTION MIN MAX UNITS

tSCLK SCLK period 2 16 1/fCLK

tSPWH, L SCLK pulse width, high and low(1) 0.8 10 1/fCLK

tDIST DIN valid to SCLK rising edge: setup time 50 ns

tDIHD Valid DIN to SCLK rising edge: hold time 50 ns

tDOPD SCLK falling edge to valid new DOUT: propagation delay(2) 100 ns

tDOHD SCLK falling edge to DOUT invalid: hold time 0 ns

Final SCLK rising edge of command to first SCLK rising edge for register read/write

tSCDL 24 1/fCLK

data. (Also between consecutive commands.)

(1) Holding SCLK low for 64 DRDY falling edges resets the serial interface.

(2) Load on DOUT = 20pF || 100kΩ.

Product Folder Links: ADS1282

CLK

SCLK

DRDY

DOUT

DIN

DGND

MCLK

SYNC

MFLAG

DGND

CAPN

CAPP

BYPAS

DGND

DVDD

DGND

RESET

PWDN

VREFP

VREFN

AVSS

AVDD

AINN1

AINP1

AINN2

AINP2

ADS1282

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

www.ti.com

7 Pin Configuration and Functions

PW Package

TSSOP-28

(Top View)

Pin Functions

NAME NO. FUNCTION DESCRIPTION

CLK 1 Digital input Master clock input

SCLK 2 Digital input Serial clock input

DRDY 3 Digital output Data ready output: read data on falling edge

DOUT 4 Digital output Serial data output

DIN 5 Digital input Serial data input

Modulator clock output; if in modulator mode:

MCLK 7 Digital I/O MCLK: Modulator clock output

Otherwise, the pin is an unused input (must be tied).

Modulator data output 1; if in modulator mode:

M1 8 Digital I/O M1: Modulator data output 1

Otherwise, the pin is an unused input (must be tied).

Modulator data output 0; if in modulator mode:

M0 9 Digital I/O M0: Modulator data output 0

Otherwise, the pin is an unused input (must be tied).

SYNC 10 Digital input Synchronize input

MFLAG 11 Digital output Modulator Over-Range flag: 0 = normal, 1 = modulator over-range

DGND 6, 12, 25, 27 Digital ground Digital ground, pin 12 is the key ground point

CAPN 13 Analog PGA outputs: Connect 10nF capacitor from CAPP to CAPN

CAPP 14 Analog PGA outputs: Connect 10nF capacitor from CAPP to CAPN

AINP2 15 Analog input Positive analog input 2

AINN2 16 Analog input Negative analog input 2

AINP1 17 Analog input Positive analog input 1

AINN1 18 Analog input Negative analog input 1

AVDD 19 Analog supply Positive analog power supply

AVSS 20 Analog supply Negative analog power supply

VREFN 21 Analog input Negative reference input

VREFP 22 Analog input Positive reference input

PWDN 23 Digital input Power-down input, active low

RESET 24 Digital input Reset input, active low

DVDD 26 Digital supply Digital power supply: +1.8V to +3.3V

BYPAS 28 Analog Sub-regulator output: Connect 1μF capacitor to DGND

Product Folder Links: ADS1282

0 50

Frequency (Hz)

-20

-40

-60

-80

-180

Amplitude (dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

8192-Point FFT

20mV

SNR = 124.2dB

10 20

Input Frequency (Hz)

100

105

110

115

120

125

130

Total Harmonic Distortion (dB)

30 40 10060 8050 70 90

V = 0.5dBFS

IN -

THD Limited by

Signal Generator

PGA = 1

PGA = 8

0 50

Frequency (Hz)

-20

-40

-60

-80

-180

Amplitude (dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

8192-Point FFT

V = 0.5dBFS, 31.25Hz

PGA = 16

THD = 122.4dB

IN -

0 50

Frequency (Hz)

-20

-40

-60

-80

-180

Amplitude (dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

8192-Point FFT

Shorted Input

SNR = 124.0dB

0 50

Frequency (Hz)

-20

-40

-60

-80

-180

Amplitude (dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

8192-Point FFT

V = 0.5dBFS, 31.25Hz

PGA = 1

THD = 124.0dB

IN -

0 50

Frequency (Hz)

-20

-40

-60

-80

-180

Amplitude (dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

8192-Point FFT

V = 20dBFS, 31.25Hz

PGA = 1

THD = 120.1dB

IN -

ADS1282

www.ti.com

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

8 Typical Characteristics

At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,

CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.

Figure 1. Output Spectrum Figure 2. Output Spectrum

Figure 3. Output Spectrum Figure 4. Output Spectrum

Figure 5. Output Spectrum Figure 6. THD vs Input Frequency

Product Folder Links: ADS1282

0.5 1.0

f (MHz)

CLK

125

124

123

122

121

120

119

Signal-to-Noise Ratio (dB)

1.5 2.0 4.53.02.5 3.5 4.0

V = 20mV

Data Rate = f /4096

IN DC

CLK

0.5 1.0

f (MHz)

CLK

-110

115

120

125

130

Total Harmonic Distortion (dB)

1.5 2.0 4.53.02.5 3.5 4.0

PGA = 8

V = 31.25Hz, 0.5dBFS

Data Rate = f /4096

CLK

0 1

V (V)

REF

130

125

120

115

110

105

100

Signal-to-Noise Ratio (dB)

2 3 5.554

PGA = 1

PGA = 8

0 1

V (V)

REF

-110

115

120

125

130

Total Harmonic Distortion (dB)

2 3 654

PGA = 1

PGA = 8

-55 -35

Temperature ( C)°

126

125

124

123

122

121

120

Signal-to-Noise Ratio (dB)

-15 5 12545 8525 65 105

V = 20mV

IN DC

-55 -35

Temperature ( C)°

-110

115

120

125

130

Total Harmonic Distortion (dB)

-15 5 12545 8525 65 105

PGA = 8

V = 31.25Hz, 0.5dBFS

IN -

ADS1282

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

www.ti.com

Typical Characteristics (continued)

At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,

CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.

Figure 7. SNR vs Temperature Figure 8. THD vs Temperature

Figure 9. SNR vs Reference Voltage Figure 10. THD vs Reference Voltage

Figure 11. SNR vs Clock Frequency Figure 12. THD vs Clock Frequency

Product Folder Links: ADS1282

0 50

Frequency (Hz)

100

120

140

160

180

Amplitude (dB)

100 150 500200 250 300 350 400 450

Shorted Input

8192-Point FFT

Adjacent Channel V = 0.5dBFS, 31.25Hz

IN -

-55 -35

Temperature ( C)°

Power (mW)

-15 5 12525 45 65 85 105

-100 -75

Input Amplitude (% Full-Scale)

Integral Nonlinearity (ppm)

-50 -25 1000 25 50 75

PGA = 8 PGA = 32

PGA = 2

-55 -35

Temperature ( C)°

Integral Nonlinearity (ppm)

-15 5 12525 45 65 85 105

10 100

Power-Supply Frequency (Hz)

140

120

100

Power-Supply Rejection (dB)

1k 10k 1M100k

DVDD

AVSS

AVDD

10 100

Input Frequency (Hz)

130

120

110

100

Common-Mode Rejection (dB)

1k 10k 1M100k

ADS1282

www.ti.com

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

Typical Characteristics (continued)

At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,

CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.

Figure 13. CMR vs Input Frequency Figure 14. Power-Supply Rejection vs Frequency

Figure 15. INL vs Input Amplitude Figure 16. INL vs Temperature

Figure 17. Crosstalk Output Spectrum Figure 18. Power vs Temperature

Product Folder Links: ADS1282

0.50

0.46

Gain Error (%)

Occurrences

0.42

0.38

0.02

0.34

0.30

0.26

0.18

0.22

0.14

Worst-Case Gain Match Relative PGA = 1 (25 Units)

0.10

0.06

-15

-14

Gain Drift (ppm/ C)°

Occurrences

-13

-12

-11

-10

-9

PGA = 1, 2, 4

PGA = 8, 64

-7

-8

-6

25 Units Based on +20 C Intervals

Over the Range of 40 C to +85 C

° °-

PGA = 32

PGA = 16

-5

-4

-3

-2

-1

-0.10

-0.08

Offset Drift ( V/ C)m °

Occurrences

-0.06

-0.04

0.10

-0.02

0.02

PGA = 8

PGA =1

0.06

0.04

0.08

25 Units Based on

+20 C Intervals

Over the Range of

40 C to +85 C

° °-

-1.2 -1.1

Gain Error (%)

Occurrences

-1.0 -0.9 -0.3-0.8 -0.7 -0.6

25 Units

-0.4-0.5

1.0 1.5

f (MHz)

CLK

Power (mW)

2.0 2.5 4.53.0 3.5 4.0

-100 -80

Offset ( V)m

Occurrences

-60 -40 100-20 0 20

25 Units

PGA = 8

PGA = 1

806040

ADS1282

SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015

www.ti.com

Typical Characteristics (continued)

At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,

CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.

Figure 19. Power vs Clock Frequency Figure 20. Offset Histogram

Figure 21. Gain Error Histogram Figure 22. Offset Drift Histogram

Figure 23. Gain Drift Histogram Figure 24. Gain Match Histogram

Product Folder Links: ADS1282

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