Texas Instruments ADS1174EVM Bedienungsanleitung

User's GuideSBAU134A – August 2008 – Revised May 2009

ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, andADS1274EVM-PDK

Figure 1. ADS1274EVM (Left) and ADS1274EVM-PDK (Right)

This user's guide describes the characteristics, operation, and use of the ADS1174EVM andADS1274EVM, both by themselves and as part of the ADS1174EVM-PDK or ADS1274EVM-PDK. Theseevaluation modules (EVMs) are evaluation boards for the ADS1274 , a 24-bit multi-channel, delta-sigmaanalog-to-digital converter (ADC), and the ADS1174 , a 16-bit version of the ADS1274. The EVM allowsevaluation of all aspects of the ADS1174 or ADS1274 devices. Complete circuit descriptions, schematicdiagrams, and bills of material are included in this document.

The following related documents are available through the Texas Instruments web site at www.ti.com .

EVM-Compatible Device Data Sheets

Device Literature Number Device Literature Number

ADS1274 SBAS367B OPA1632 SBOS286AADS1174 SBAS373A SN74LVC2G157 SCES207KREF5025 SBOS410 TPS73018 SBVS054HREF3125 SBVS046C TPS65131 SLVS493BOPA2350 SBOS099C PCA9535 SCPS129H

ADCPro is a trademark of Texas Instruments.Microsoft, Windows are registered trademarks of Microsoft Corporation.SPI is a trademark of Motorola.I

C is a trademark of NXP Semiconductors.NI-VISA is a trademark of National Instruments.All other trademarks are the property of their respective owners.

SBAU134A – August 2008 – Revised May 2009 ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK 1Submit Documentation Feedback

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Contents1 EVM Overview ............................................................................................................... 32 Analog Interface .............................................................................................................. 43 Digital Interface .............................................................................................................. 44 Power Supplies .............................................................................................................. 65 Voltage Reference ........................................................................................................... 76 Power-Down, Mode and Format Control ................................................................................. 87 Clock Source ................................................................................................................. 88 EVM Operation ............................................................................................................... 99 ADS1274EVM-PDK Kit Operation ....................................................................................... 1210 Evaluating Performance with the ADCPro Software ................................................................... 2411 Schematics and Layout .................................................................................................... 28
List of Figures
1 ADS1274EVM (Left) and ADS1274EVM-PDK (Right) .................................................................. 12 Connector J2 ................................................................................................................. 53 Connectors J15, J16 ........................................................................................................ 74 Connector J1 ................................................................................................................. 75 Switch S1 ..................................................................................................................... 76 Jumper J19 ................................................................................................................... 97 Amplifier Selection Switches ............................................................................................... 98 ADS1274EVM Default Jumper Locations ............................................................................... 119 MMB0 Initial Setup ........................................................................................................ 1310 Connecting ADS1274EVM to MMB0 ................................................................................... 1411 Connecting an AC Adapter ............................................................................................... 1512 Laboratory Power-Supply Connection ................................................................................... 1613 NI-VISA Driver Installation ................................................................................................ 1714 NI-VISA Driver Installation Question .................................................................................... 1815 NI-VISA Driver Installing .................................................................................................. 1816 NI-VISA Driver Complete Installation ................................................................................... 1917 NI-VISA Driver Verification Using Device Manager ................................................................... 1918 ADCPro Software Start-up Display Window ............................................................................ 2019 ADS1274EVM-PDK Plug-In Display Window........................................................................... 2120 Install New Driver Wizard Screen 1 ...................................................................................... 2221 Install New Driver Wizard Screen 2 ...................................................................................... 2222 Install New Driver Wizard Screen 3 ...................................................................................... 2323 Install New Driver Wizard Screen 4 ...................................................................................... 2324 Install New Driver Wizard Screen 5 ...................................................................................... 2425 USBSytx Driver Verification Using Device Manager .................................................................. 2426 Channel Enable............................................................................................................. 2527 Manual Channel Control ................................................................................................... 2528 Clock Settings and Mode .................................................................................................. 2629 Operating Mode ............................................................................................................ 2630 Output Data Format ........................................................................................................ 2731 Progress Bar While Collecting Data ..................................................................................... 27
List of Tables
1 J9/J7:Analog Interface Pinout .............................................................................................. 42 J5: Serial Interface Pins ..................................................................................................... 43 J3 Configuration: Power-Supply Input .................................................................................... 64 J15 +10V Selection .......................................................................................................... 65 J16 –10V Selection .......................................................................................................... 66 List of Switches ............................................................................................................. 117 Operating Modes: Clock Frequency ..................................................................................... 26
2ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK SBAU134A – August 2008 – Revised May 2009Submit Documentation Feedback

1 EVM Overview

1.1 Features

1.2 Introduction

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EVM Overview

8 ADS1174EVM/ADS1274EVM Bill of Materials ......................................................................... 28

ADS1174EVM/ADS1274EVM Features:•Contains all support circuitry needed for the ADS1174/ADS1274•+10V and –10V generated from the +5V supply or supplied externally•Voltage reference options: external or onboard•Clock options: External clock source or 27MHz onboard crystal oscillator•GPIO access•Compatible with the TI Modular EVM System

ADS1174EVM-PDK/ADS1274EVM-PDK Features:•Easy-to-use evaluation software for Microsoft

Windows

XP•Data collection to text files•Built-in analysis tools including scope, FFT, and histogram displays•Complete control of board settings•Easily expandable with new analysis plug-in tools from Texas Instruments

For use with a computer, the ADS1174EVM-PDK or ADS1274EVM-PDK is available. This kit combinesthe ADS1174EVM/ADS1274EVM board with the DSP-based MMB0 motherboard, and includes ADCPro™software for evaluation.

The MMB0 motherboard allows the ADS1174EVM/ADS1274EVM to be connected to the computer via anavailable USB port. This manual shows how to use the MMB0 as part of theADS1174EVM-PDK/ADS1274EVM-PDK, but does not provide technical details about the MMB0 itself.

ADCPro™ is a program for collecting, recording, and analyzing data from ADC evaluation boards. It isbased on a number of plug-in programs, so it can be expanded easily with new test and data collectionplug-ins. The ADS1174EVM-PDK/ADS1274EVM-PDK is controlled by a plug-in running in ADCPro. Formore information about ADCPro, see the ADCPro™ Analog-to-Digital Converter Evaluation SoftwareUser's Guide (literature number SBAU128 ), available for download from the TI web site.

This manual covers the operation of both the ADS1174EVM/ADS1274EVM and theADS1174EVM-PDK/ADS1274EVM-PDK. Throughout this document, the abbreviation EVM and the termevaluation module are synonymous with the ADS1174EVM and the ADS1274EVM. For clarity of reading,the remainder of this manual will refer only to the ADS1274EVM or ADS1274EVM-PDK, but operation ofthe EVM and kit for the ADS1174 is identical, unless otherwise noted.

The ADS1274EVM is an evaluation module built to the TI Modular EVM System specification. It can beconnected to any modular EVM system interface card.

The ADS1274EVM is available as a stand-alone printed circuit board (PCB) or as part of theADS1274EVM-PDK, which includes an MMB0 motherboard and related software. As a stand-alone PCB,the ADS1274EVM is useful for prototyping designs and firmware.

Note that the ADS1274EVM has no microprocessor and cannot run software. To connect it to a computer,some type of interface is required.

SBAU134A – August 2008 – Revised May 2009 ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK 3Submit Documentation Feedback

2 Analog Interface

3 Digital Interface

3.1 Serial Data Interface

Analog Interface

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For maximum flexibility, the ADS1274EVM is designed for easy interfacing to multiple analog sources.Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,dual-row, header/socket combination at J9. This header/socket provides access to the analog input pins ofthe ADS1274. Consult Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of matingconnector options. These signals can also be connected to the terminal block J7.

Most of the pins on J7 and J9 are directly connected, with no filtering or protection. Use appropriatecaution when handling these pins. Table 1 summarizes the pinouts for analog interfaces J9 and J7.

Table 1. J9/J7:Analog Interface Pinout

Pin Number Signal Description

J9.1, J7-2 A1N AINN1, ADS1274J9.2, J7-3 A1P AINP1, ADS1274J9.3, J7-4 A2N AINN2, ADS1274J9.4, J7-5 A2P AINP2, ADS1274J9.5, J7-6 A3N AINN3, ADS1274J9.6, J7-7 A3P AINP3, ADS1274J9.7, J7-8 A4N AINN4, ADS1274J9.8, J7-9 A4P AINP4, ADS1274J9.18 EXTREFN External Reference source input(– side of differential input)J9.20 EXTREFP External Reference source input(+ side of differential input)J9.10-16 (even) UnusedJ9.15 UnusedJ9.9-19 (odd), J7-1 AGND Analog ground connections (except J1.15)

The ADS1274EVM is designed to easily interface with multiple control platforms. Samtec part numbersSSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socketcombination at J5. This header/socket provides access to the digital control and serial data pins of theADC. Consult Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of matingconnector options.

All logic levels on J5 are 3.3V CMOS, except for the I

C™ pins. These pins conform to 3.3V I

C rules.Table 2 describes the J5 serial interface pins.

Table 2. J5: Serial Interface Pins

Pin No. Pin Name Signal Name I/O Type Pullup Function

J5.1 CNTL SYNC In HighJ5.2 GPIO0 MODE0 In HighJ5.3 CLKX SCLK In None ADS1274 SPI™clockJ5.4 DGND DGND In/Out None Digital GroundJ5.5 CLKR CLKR Out None SCLK clockJ5.6 GPIO1 MODE1 In HighJ5.7 FSX /DRDY/FSYNC In/Out LowJ5.8 GPIO2 FORMAT0 In High

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3.2 Data Output

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Digital Interface

Table 2. J5: Serial Interface Pins (continued)

Pin No. Pin Name Signal Name I/O Type Pullup Function

J5.9 FSR /DRDY/FSYNC In/Out NoneJ5.10 DGND DGND In/Out None Digital GroundJ5.11 DX DIN In None ADS1274 SPI datainJ5.12 GPIO3 FORMAT1 In HighJ5.13 DR DOUT1 Out None ADS1274 data outJ5.14 GPIO4 FORMAT2 In NoneJ5.15 /INT /DRDY/FSYNC Out NoneJ5.16 SCL SCL I

C n/a I

C clockJ5.17 TOUT CLK In None Can be used toprovide a clock froma processorJ5.18 DGND DGND In/Out None Digital GroundJ5.19 GPIO5 CLK Select NoneJ5.20 SDA SDA I

C n/a I

C data

Many pins on J5 have weak pull-up/pull-down resistors. These resistors provide default settings for manyof the control pins. Many pins on J5 correspond directly to ADS1274 pins. See the ADS1274 product datasheet for complete details on these pins.

Most data communications are directed through DOUT1. The data from all eight channels can beobserved on the DOUT1 pin using the TDM mode. That is the signal used by the ADS1274EVM-PDK toread back and display all the channels. All the data output signals (DOUT1 to DOUT4) can be monitoredon J2. Figure 2 illustrates the pinout for J2.

Figure 2. Connector J2

SBAU134A – August 2008 – Revised May 2009 ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK 5Submit Documentation Feedback

4 Power Supplies

4.1 Bipolar Power Options

Power Supplies

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J3 is the power-supply input connector. Table 3 lists the configuration details for J3. Analog inputs to theADC can be applied directly to the device (see Section 8.1 ,Analog Input), bypassing the onboardamplifiers, and in this case only +5V and +3.3V are required to power the EVM. If the amplifiers are used,an additional bipolar supply is needed to power them. The EVM includes a switching power supply togenerate a +10V and –10V supply. For optimum noise performance, the external supplies (+VA and –VA)should be used.

Table 3. J3 Configuration: Power-Supply Input

Pin No. Pin Name Function Required

J3.1 +VA +10V to +15V Yes, unless onboard +10V isused.J3.2 –VA –10V to –15V Yes, unless onboard –10V isused.J3.3 +5VA +5V analog supply AlwaysJ3.4 –5VA –5V analog supply NoJ3.5 DGND Digital ground input YesJ3.6 AGND Analog ground input YesJ3.7 +1.8VD 1.8V digital supply NoJ3.8 +3.3VD 3.3V digital supply AlwaysJ3.9 VD1 Not used NoJ3.10 +5VD +5V Used to generate +10V/–10V

The 1.8V for DVDD comes from the voltage regulator U16 using 3.3V as the source voltage input.

All of the power supplies AVDD (+5V), DVDD (1.8V), and IOVDD (3.3V) have corresponding jumpers J10,J11(AVDD), J13(DVDD) and J14(IOVDD) that can be replaced with a current meter to measure therespective supply currents.

J15 and J16 require a jumper to select the voltage used by the onboard amplifiers. The external voltagescan range from 10V to 15V. The onboard voltage is always 10V. Table 4 and Table 5 list the options forJ15 and J16, respectively. Figure 3 shows the pinout for connectors J15 and J16.

Table 4. J15 +10V Selection

Jumper Name Function

1-2 (OB) +10V Select the +10V that is generated on theEVM2-3 (EXT) +VA Select the external +VA voltage

Table 5. J16 –10V Selection

Jumper Name Function

1-2 –10V Select the –10V that is generated on theEVM2-3 –VA Select the external –VA voltage

ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK6 SBAU134A – August 2008 – Revised May 2009Submit Documentation Feedback

5 Voltage Reference

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Voltage Reference

Figure 3. Connectors J15, J16

The ADS1274EVM has three sources for the reference voltage. Jumper J1 can select the voltage fromeither the REF3125(U1) or REF5025(U2). The reference from either source is filtered and buffered byU3A. Switch S1 chooses either the onboard reference or the external reference voltage that is connectedto the reference pins of J9. Figure 4 illustrates the pinout for connector J1. Figure 5 shows switch S1 as itappears on the EVM.

Figure 4. Connector J1

Figure 5. Switch S1

SBAU134A – August 2008 – Revised May 2009 ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK 7Submit Documentation Feedback

6 Power-Down, Mode and Format Control

7 Clock Source

7.1 Usage in PDK

7.2 Usage as a Stand-Alone EVM

Power-Down, Mode and Format Control

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The ADS1274 has several pins to control power-down of individual channels, and mode and format for thedigital interface. These pins are controlled on the EVM either through software or hardware (usingswitches S10 and S11).

For users of the ADS1274EVM as a stand-alone module, these pins may be pulled high or low throughDIP switches S10 and S11. Refer to the ADS1274 product data sheet for complete details on these pinsand which state sets which options.

For use in the ADS1274EVM-PDK, the state of these pins is controlled by software, using the I

C portexpander on the EVM. When used in the ADS1274EVM-PDK, DIP switches S10 and S11 must all beswitched so that they are down, toward the center of the board. The ADS1274EVM-PDK software willcheck at startup to verify that these switches are set correctly, and will generate an error message if theyare not. However, it cannot detect if the switches are changed after startup.

CAUTION

When using the EVM as part of the ADS1274EVM-PDK, DIP switches S10 andS11 must all be switched so that they are down, toward the center of the board.Failure to do so may damage the EVM.

The ADS1274 clock can come from one of several sources: the onboard 27MHz crystal oscillator, a clocksupplied by a processor on the TOUT pin (J5.17), or an external clock source connected to J18.1 (ground)and J18.2 (signal).

If the onboard 27MHz oscillator is selected, the device can be run in the high-speed mode, thehigh-resolution mode, the low-power mode, or low-speed mode with CLKDIV set to 1. If the performanceof the device must be explored with CLKDIV set to 0 in the low-power and low-speed modes, an externalclock must be provided to the board, either using the TOUT connection or having an external clock sourceconnected to J18. The same is true if frequencies other than the 27MHz provided by the onboard oscillatormust be investigated.

If using the ADS1274EVM as part of the ADS1274EVM-PDK, J19 should not have any pins shorted.Remove any shorting blocks on jumper J19. The ADS1274EVM-PDK software will allow selection of theclock source under software control (this option is accomplished by using port 05 of the I

C expanderU17). The software allows selection of the onboard 27MHz oscillator, or a clock provided by a PLL on theMMB0 which directly drives the appropriate CLK pins of the interface, or an external, customer suppliedclock. If an external clock is selected with the software, this clock must be provided on J18. Note that if theexternal clock is selected and no clock is provided, the software may hang waiting for data from theconverter.

If using the EVM in your own system and not with the PDK hardware and software, observe the followingrecommendations:

•J17 should be removed if the external clock source is used and the TOUT pin is still driven by aprocessor in order to avoid conflicts.•Jumper J19 can be used to always select the 27MHz crystal (IOVDD position) or allow theonboard/external clock selection to be controlled by GPIO5 (J5.19) as shown in Figure 6 .

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8 EVM Operation

8.1 Analog Input

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EVM Operation

Figure 6. Jumper J19

The following section provides information on the analog input, digital control, and general operatingconditions of the ADS1274EVM.

The analog input sources (channels 1-4) can be applied directly to J9 (top or bottom side) or throughsignal-conditioning modules available for the the modular EVM system. Terminal block J7 is connected inparallel with the analog signal connections to J9.

Each input signal can be selected to connect directly to the analog inputs of the ADS1274 or they can usethe OPA1632 buffers that are provided. Switches S2-5 can be switched away from the ADS1274 to selectthe Terminal Block (TBK) or towards the ADS1274 to select the Amplifier (AMP) for the analog inputs 1through 4 as shown in Figure 7 .

Figure 7. Amplifier Selection Switches

SBAU134A – August 2008 – Revised May 2009 ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK 9Submit Documentation Feedback

8.2 Digital Control

8.3 ADS1274EVM-PDK Power Supply

EVM Operation

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The digital control signals can be applied directly to J5 (top or bottom side). The modular ADS1274EVMcan also be connected directly to a DSP or microcontroller interface board, such as the 5-6KINTERFACEor HPA-MCUINTERFACE boards available from Texas Instruments, or the MMB0 if purchased as part ofthe ADS1274EVM-PDK. For a list of compatible interface and/or accessory boards for the EVM or theADS1274, see the relevant product folder on the TI web site. Some of the digital signals are controlleddirectly with pins on J5. Other signals such as the Power Down controls can only be controlled with slideswitches or by U17 and U18 that are set up and read using the I

C signals on pins 16 and 18 of J5. TheFormat and Mode pins can be controlled by all three methods (slide switches, GPIO pins on J5, and theI

C control from U17).

The ADS1274 allows the serial interface to be used in two different formats: an SPI-compatible mode anda frame-sync format. Switch S12 can be used to switch between these two formats. The left position,marked SPI, selects the SPI format. In this format, the signals are connected in this configuration:•The SCLK input of the converter is driven by the serial port signal CLKX, pin J5.3.•The signal from the selected source for the clock (see Section 7 ,Clock Source) is connected to theCLKR pin (J5.5) allowing the serial port of a processor to be synchronized to the converter masterclock.

•The signal from the selected clock source is routed to the CLK input of the converter.•Port P10 of the I

C port expander U18 is connected to a logic high level, so that the position of switchS12 can be read back by software.

The right position of S12, marked FS, selects the frame-sync format. In this format, the signals areconnected in this configuration:•The SCLK input of the converter is driven by the serial port signal CLKR, pin J5.5.•The signal from the selected clock source is connected to the CLKX pin (J5.3), allowing the serial portof a processor to be synchronized to the converter master clock.•The CLK input of the converter is driven by the CLKR signal (J5.5). This connection ensures that theCLK and SCLK signals have the same phase and the correct ratio as outlined in the data sheet of thedevice.

•Port P10 of the I

C port expander U18 is connected to a logic low level, so that the position of switchS12 can be read back by software.

For use in the ADS1274EVM-PDK, S12 must be in the right (FS) position, which is the default factorysetting.

Switching to SPI format will allow the EVM to connect to any SPI-compatible processor that does notsupport the frame-sync mode. If this format is selected, keep in mind that the high-speed mode will notwork at full speed (32.768MHz) because of the limitations outlined in the device product data sheet.

The ADS1274EVM can either be powered by an AC adapter or by applying the 5V, +10V and –10V to theconnectors on the MMB0 board. The MMB0 board will provide the 5V and 3.3V to the ADS1274EVMalong with the +10V and –10V signals. Because the circuitry is provided on the ADS1274EVM to generate+10V and –10V, the complete system can be powered from the supplied AC adapter that supplies +6Vand 3A.

ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK10 SBAU134A – August 2008 – Revised May 2009Submit Documentation Feedback

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