Texas Instruments TPA3129D2EVM Bedienungsanleitung

SLOU470–September 2017

TPA3129D2 Evaluation Module

User's Guide

SLOU470–September 2017

TPA3129D2 Evaluation Module

This user’s guide describes the operation of the TPA3129D2EVM. The document also provides design

information such as schematic, BOM, and PCB layout.

Contents

1 Hardware Overview.......................................................................................................... 2

2 Operation ..................................................................................................................... 3

3 Board Layouts, Bill of Materials, and Schematic ........................................................................ 6

List of Figures

1 TPA3129D2EVM Board..................................................................................................... 2

2 TPA3129D2EVM Top Overlay............................................................................................. 6

3 TPA3129D2EVM Bottom Overlay ......................................................................................... 6

4 TPA3129D2EVM Schematic ............................................................................................... 9

List of Tables

1 TPA3129D2EVM Specification............................................................................................. 2

2 Power Requirements........................................................................................................ 3

3 TPA3129D2EVM Setting 1 ................................................................................................. 4

4 TPA3129D2EVM Setting 2 ................................................................................................. 4

5 TPA3129D2EVM Setting 3 ................................................................................................. 5

6 TPA3129D2EVM Parts List................................................................................................. 7

Trademarks

All trademarks are the property of their respective owners.

Hardware Overview

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TPA3129D2 Evaluation Module

1 Hardware Overview

The TPA3129D2 EVM customer evaluation module demonstrates the TPA3129D2 integrated circuit from

Texas Instruments (TI). The TPA3129D2 is a 30-W (per channel), efficient stereo digital amplifier power

stage for driving 2 bridge-tied speakers or a single parallel bridge-tied load. This document covers EVM

specifications and design documentation.

Figure 1 illustrates the EVM board. Table 1 lists EVM specifications.

Figure 1. TPA3129D2EVM Board

Table 1. TPA3129D2EVM Specification

Key Parameters Value

Power supply voltage 4.5 V to 26 V

Number of channels 2 bridge-tied load (BTL) Stereo

Load impedance 5.6 Ωto 8 Ω

Output power BTL 15 W per channel

Output power PBTL 30 W

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Operation

SLOU470–September 2017

TPA3129D2 Evaluation Module

2 Operation

This section describes the TPA3129D2EVM board in regards to the power supply and system interfaces.

Information regarding handling and unpacking, absolute operating conditions, and a description of the

factory default switch and jumper configurations is provided.

The following is a step-by-step guide to configuring the TPA3129D2EVM for device evaluation:

2.1 Electrostatic Discharge Warning

Many of the components on the TPA3129D2EVM are susceptible to damage by electrostatic discharge

CAUTION

Failure to observe ESD handling procedures may result in damage to EVM

components.

2.2 Unpacking the EVM

On opening the TPA3129D2EVM package, ensure that the following item is included:

1 piece TPA3129D2EVM board using one TPA3129D2 device

If the EVM board is missing, contact the Texas Instruments Product Information Center nearest you to

inquire about a replacement.

2.3 Power Supply Setup

A single power supply or separate PVCC or AVCC is required to power up the EVM. Since most of the

pins are PVCC-compliant, the PVCC supply can also be used to power the analog supply (AVCC) and to

pullup the logic pins for shutdown (SD) control, and fault detection (FAULT).

Table 2. Power Requirements

Description Voltage Range Current Requirement Minimum Wire Size

PVCC or AVCC 4.5 to 26 V 8 A 24 AWG

CAUTION

Applying voltages above the limitations given in Table 2 may cause permanent

damage to your hardware.

2.4 Evaluation Module Preparations

Prepare the EVM using the following steps:

1. Ensure that the external power source is set to OFF.

2. Connect the external regulated power supply adjusted from 4.5 V to 26 V to the module PVCC and

GND banana jacks taking care to observe marked polarity.

Operation

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2.5 Inputs and Outputs

Make the following input and output connections:

1. Connect audio inputs, either differential or single-ended, to the LIN and RIN RCA phono plugs for BTL

operation. To enable the individual channel shutdown feature, tie RINP and RINN directly to GND

(without capacitors) and OUTPL and OUTNL should be working normally in BTL configuration. For

PBTL operation, apply a single input, differential or single-ended, to the RIN RCA phono plug and tie

LINP and LINN directly to GND (without capacitors).

2. For a BTL configuration, connect a load across the outputs (OUTL+ and OUTL–) and (OUTR+ and

OUTR–). For PBTL configuration, connect a single load from one of the left speaker jacks to one of the

right speaker jacks, depending on how the filters are loaded.

2.6 Power Up

When powering up the EVM, use the following steps:

1. Verify the correct voltage and input polarity and turn the external power supplies ON. The EVM should

begin operation.

2. Adjust the audio source for the correct volume.

2.7 Recommended Settings

This section contains the recommended settings for stereo, single-channel, and mono output.

Table 3 lists the settings for a single-ended input with auto recovery, Plimit, and BTL (stereo output).

Table 3. TPA3129D2EVM Setting 1

Setting Description

J6 (RIN) R channel audio input

J9 (LIN) L channel audio input

JP1 (GNDR+) and JP3 (GNDR–), set to OUT R channel on

JP4 (GNDL+) and JP6 (GNDL–), set to OUT L channel on

JP2 (RGND), set to IN Single-ended input (R channel)

JP5 (LGND), set to IN Single-ended input (L channel)

JP7, set to IN Set PLIMIT

R4 Change PLIMIT voltage value

JP8 (SD = FAULT), set to IN Auto-recovery mode

J11 (MODESEL = L) Low idle-loss mode

Table 4 lists the settings for a single-ended input with auto recovery, Plimit, and BTL (single-channel

output).

Table 4. TPA3129D2EVM Setting 2

Setting Description

J6 (RIN) No audio input

J9 (LIN) L channel audio input

JP1 (GNDR+) and JP3 (GNDR–), set to IN R channel off

JP4 (GNDL+) and JP6 (GNDL–), set to OUT L channel on

JP5 (LGND), set to IN Single-ended input (L channel)

JP7, set to IN Set PLIMIT

R4 Change PLIMIT voltage value

JP8 (SD = FAULT), set to IN Auto-recovery mode

J11 (MODESEL = L) Low idle-loss mode

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Operation

SLOU470–September 2017

TPA3129D2 Evaluation Module

Table 5 lists the settings for a single-ended input with auto recovery, Plimit, and PBTL (mono output).

Table 5. TPA3129D2EVM Setting 3

Setting Description

J6 (RIN) R channel audio input

J9 (LIN) No audio input

JP1 (GNDR+) and JP3 (GNDR–), set to OUT R channel on

JP4 (GNDL+) and JP6 (GNDL–), set to IN L channel off, PBTL mode

JP2, set to IN Single-ended input (R channel)

JP7, set to IN Set PLIMIT

R4 Change PLIMIT voltage value

JP8 (SD = FAULT), set to IN Auto-recovery mode

J11 (MODESEL = L) Low idle-loss mode

2.8 Separate PVCC or AVCC Supply Support

By supplying a voltage of AVCC which is lower than PVCC (for example, PVCC = 24 V and AVCC = 12

V), the power dissipation on the internal LDO is reduced. This gives customers the flexibility to choose

between extreme low-idle current mode (J3, 1 and 2 set to IN, with separate AVCC) and single-power

supply mode (J3, 2 and 3 set to IN, without AVCC).

Board Layouts, Bill of Materials, and Schematic

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TPA3129D2 Evaluation Module

3 Board Layouts, Bill of Materials, and Schematic

3.1 TPA3129D2EVM Board Layouts

Figure 2 and Figure 3 illustrate the board layouts for the EVM.

Figure 2. TPA3129D2EVM Top Overlay

Figure 3. TPA3129D2EVM Bottom Overlay

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Board Layouts, Bill of Materials, and Schematic

SLOU470–September 2017

TPA3129D2 Evaluation Module

3.2 Bill of Materials

Table 6 displays the BOM for this EVM.

Table 6. TPA3129D2EVM Parts List

Designator Qty Value Description Package

Reference Part Number Manufacturer Alternate Part Number Alternate

Manufacturer

!PCB1 1 Printed Circuit Board AAP067 Any - -

C1, C13,

C20, C25 4 0.68uF CAP, CERM, 0.68 µF, 50 V, +/- 10%, X7R, 1206 1206 GRM31MR71H684KA88L Murata

C2, C14,

C21, C26 4 0.01uF CAP, CERM, 0.01 µF, 50 V, +/- 10%, X7R, 0603 0603 GRM188R71H103KA01D Murata

C3, C9 2 220uF CAP, AL, 220 µF, 35 V, +/- 20%, 0.09 ohm, TH 10x12.5mm EEU-FC1V221 Panasonic

C4, C10 2 0.1uF CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0603 0603 GCM188R71H104KA57D Murata

C5, C11 2 1000pF CAP, CERM, 1000 pF, 50 V, +/- 5%, C0G/NP0, 0603 0603 GRM1885C1H102JA01D Murata

C6 1 10uF CAP, CERM, 10 µF, 35 V, +/- 10%, X7R, 1210 1210 GRM32ER7YA106KA12L Murata

C7, C12,

C19, C22 4 1uF CAP, CERM, 1 µF, 16 V, +/- 10%, X7R, 0603 0603 GRM188R71C105KA12D Murata

C8 1 1uF CAP, CERM, 1 µF, 30 V, +/- 10%, X7R, 0603 0603 C1608X7R1V105K080AC TDK

C15, C16,

C17, C18 4 0.22uF CAP, CERM, 0.22 µF, 25 V, +/- 10%, X7R, 0603 0603 GRM188R71E224KA88D Murata

C23, C24 2 1uF CAP, CERM, 1 µF, 16 V, +/- 10%, X7R, 0805 0805 C0805C105K4RACTU Kemet

C27 1 47pF CAP, CERM, 47 pF, 50 V, +/- 5%, C0G/NP0, 0603 0603 GRM1885C1H470JA01D Murata

C28, C29,

C30, C31 4 330pF CAP, CERM, 330 pF, 50 V, +/- 5%, C0G/NP0, 0603 0603 GRM1885C1H331JA01D Murata

H1, H2, H3,

H4 4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead Screw NY PMS 440 0025 PH B&F Fastener Supply

H5, H6, H7,

H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone - -

J1, J2, J4,

J8 4 Binding Post, RED, TH 11.4x27.2m

m7006 Keystone

J3, J11, J12,

J13, J14 5 Header, 100mil, 3x1, Gold, TH PBC03SAA

NPBC03SAAN Sullins Connector

Solutions

J5, J7, J10 3 Binding Post, BLACK, TH 11.4x27.2m

m7007 Keystone

J6 1 RCA Jack, Red, R/A, TH PC Mount

Phono Jack-

Red, TH

971 Keystone

J9 1 RCA Jack, White, R/A, TH PC Mount

Phono Jack-

White, TH

970 Keystone

JP1, JP2,

JP3, JP4,

JP5, JP6,

JP7, JP8

8 Header, 100mil, 2x1, Gold, TH Sullins

100mil, 1x2,

230 mil

above

insulator

PBC02SAAN Sullins Connector

Solutions

L1, L2, L3,

L4 4 10uH Inductor, Ferrite, 10 µH, 4.4 A, 23 ohm, SMD 12.8x12.8m

m#B953AS-100M=P3 Murata Toko

Q1 1 40 V Transistor, NPN, 40 V, 0.6 A, SOT-23 SOT-23 MMBT2222ALT1G ON Semiconductor

R1, R2, R3,

R12 4 3.3 RES, 3.3, 5%, 0.1 W, 0603 0603 CRCW06033R30JNEA Vishay-Dale

Board Layouts, Bill of Materials, and Schematic

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Table 6. TPA3129D2EVM Parts List (continued)

Designator Qty Value Description Package

Reference Part Number Manufacturer Alternate Part Number Alternate

Manufacturer

R4 1 100k TRIMMER, 100k ohm, 0.5W, TH 375x190x37

5mil 3386P-1-104LF Bourns

R5 1 100k RES, 100 k, 1%, 0.125 W, 0805 0805 CRCW0805100KFKEA Vishay-Dale

R6, R7 2 20.0k RES, 20.0 k, 1%, 0.125 W, 0805 0805 CRCW080520K0FKEA Vishay-Dale

R8 1 4.70k RES, 4.70 k, 0.1%, 0.1 W, 0603 0603 RG1608P-472-B-T5 Susumu Co Ltd

R9, R11,

R13, R18,

R19, R20,

R21

7 100k RES, 100k ohm, 1%, 0.1W, 0603 0603 RC0603FR-07100KL Yageo America

R10 1 499k RES, 499 k, 1%, 0.1 W, 0603 0603 RC0603FR-07499KL Yageo America

R14, R15,

R16, R17 4 10 RES, 10, 5%, 0.125 W, 0805 0805 CRCW080510R0JNEA Vishay-Dale

S1, S2 2 Switch, Tactile, SPST-NO, 0.05A, 12V, SMT Switch,

4.4x2x2.9

TL1015AF160QG E-Switch

SH1, SH2,

SH3, SH4,

SH5, SH6,

SH7, SH8,

SH9

9 1x2 Shunt, 100mil, Gold plated, Black Shunt 969102-0000-DA 3M SNT-100-BK-G Samtec

TP1, TP2,

TP3, TP4,

TP5, TP6,

TP7, TP8

8 Orange Test Point, Miniature, Orange, TH Orange

Miniature

Testpoint

5003 Keystone

TP9, TP10,

TP11, TP12 4 Test Point, Miniature, Black, TH Black

Miniature

Testpoint

5001 Keystone

U1 1 TPA3129D2, DAP0032A DAP0032A TPA3129D2DAPR Texas Instruments Texas Instruments

FID1, FID2,

FID3 0 Fiducial mark. There is nothing to buy or mount. Fiducial N/A N/A

Notes: Unless otherwise noted in the Alternate Part Number and/or Alternate Manufacturer columns, all parts may be substituted with equivalents.

1µF

C19

LIN

1µF

C22

GND

IN = PBTL

OUT = BTL

JP4

GNDL+

JP6

GNDL-

GND

RIN

1µF

C12

GND

JP1

GNDR+

JP3

GNDR-

GND

RINP

RINN

LINP

LINN

LINP

LINN

RINN

RINP

IN = R Channel OFF

OUT = R Channel ON

AVOIDANCE

J12

PVCC

100k

R19

PVCC

100k

R20

PVCC

100k

R21

J13

J14

GND

AM0

AM1

AM2

AM0

AM1

AM2

J11

MODSEL

PVCC

100k

GND

SHUTDOWN

GND

PVCC

499k

R10

JP8

TP3

SDz

TP5

PLIMIT

TP8

FAULTz

TP7 SYNC

GND

4.70k

47pF

C27

GND

20.0k

1µF

C24

GND

Red

PVCC

Black

GND

PVCC

1µF

GND

Red

AVCC

GND

10µF

AVCC-SEL

GND

AVCC

AVCC-IN

220µF

35V

0.1µF

50V

1000pF

50V

GND GND GND

220µF

35V

0.1µF

50V

C10

1000pF

50V

C11

GND GND GND

PVCC

10µH 4.4A

0.68µF

50V

0.01µF

50V

3.3

GND

Red

ROUT+

GND

TP1

R+

0.68µF

50V

C13

0.01µF

50V

C14

3.3

GND

TP2

R-

0.68µF

50V

C20

0.01µF

50V

C21

3.3

GND

Red

LOUT+

GND

TP4

L+

0.68µF

50V

C25

0.01µF

50V

C26

3.3

R12

GND

TP6

L-

Black

ROUT-

Black

J10

LOUT-

0.22µF 25V

C15

0.22µF 25V

C16

0.22µF 25V

C17

0.22µF 25V

C18

OUTPR

OUTNR

OUTNL

OUTPL

OUTR+

OUTR-

OUTL+

OUTL-

330pF

50V

C28

R14

GND

330pF

50V

C29

R15

GND

330pF

50V

C30

R16

GND

330pF

50V

C31

R17

GND

100k

PLIMIT

MUTE

GVDD

100k

1µF

C23

GND

JP7

PLIMIT

20.0k

GND

FAULT

SD SD FAULT

PVCC

100k

R11

MUTE

GND

100k

R18

GND

MUTE

MUTE-SW

PVCC

100k

R13

10µH 4.4A

MODSEL

SDZ

FAULTZ 3

RINP

RINN

PLIMIT

GVDD

GAIN/SLV

GND 9

LINP

LINN

MUTE

AM2

13 AM1

14 AM0

SYNC

AVCC

PVCC

BSNL 20

OUTNL 21

GND 22

OUTPL 23

BSPL 24

GND 25

BSNR 26

OUTNR 27

GND 28

OUTPR 29

BSPR 30

PVCC

PAD 33

TPA3129D2DAPR

JP2

RGND

JP5

LGND

TP9

GND

TP10

GND

TP11

GND

TP12

GND

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Board Layouts, Bill of Materials, and Schematic

SLOU470–September 2017

TPA3129D2 Evaluation Module

3.3 TPA3129D2EVM Schematic

Figure 4 illustrates the schematics for the TPA3129D2EVM.

Figure 4. TPA3129D2EVM Schematic

STANDARD TERMS FOR EVALUATION MODULES

1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or

documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance

with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.

1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility

evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not

finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For

clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions

set forth herein but rather shall be subject to the applicable terms that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,

or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production

system.

2Limited Warranty and Related Remedies/Disclaimers:

2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License

Agreement.

2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM

to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by

neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have

been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications

or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control

techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.

User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)

business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.

2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit

User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty

period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or

replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be

warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day

warranty period.

3Regulatory Notices:

3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:

FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software

associated with the kit to determine whether to incorporate such items in a finished product and software developers to write

software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or

otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition

that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.

Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must

operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.

3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTION

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not

cause harmful interference, and (2) this device must accept any interference received, including interference that may cause

undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to

operate the equipment.

FCC Interference Statement for Class A EVM devices

NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of

the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is

operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not

installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.

Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to

correct the interference at his own expense.

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