Alphi CPCI-QIPC Bedienungsanleitung

CPCI-QIPC

Intelligent IP CARRIER for CPCICPCI™ systems

Up to Four IndustryPack®Modules

Dual Ported SRAM between CPCI and DSP C31

REFERENCE MANUAL

739-11-000-4000

Version 1.1

May 1998

ALPHI TECHNOLOGY CORPORATION

6202 S. Maple Avenue #120

Tempe, AZ 85283 USA

Tel: (602) 838-2428

Fax: (602) 838-4477

CPCI-QIPC REFERENCE MANUAL

ALPHI TECHNOLOGY CORP. Page ii Ver 1.1

Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

NOTICE

The information in this document has been carefully checked and is believed to be

entirely reliable. While all reasonable efforts to ensure accuracy have been taken in the

preparation of this manual, ALPHI TECHNOLOGY assumes no responsibility resulting

from omissions or errors in this manual, or from the use of information contain herein.

ALPHI TECHNOLOGY reserves the right to make any changes, without notice, to this or

any of ALPHI TECHNOLOGY’s products to improve reliability, performance, function or

design.

ALPHI TECHNOLOGY does not assume any liability arising out of the application or use

of any product or circuit described herein; nor does ALPHI TECHNOLOGY convey any

license under its patent rights or the rights of others.

ALPHI TECHNOLOGY CORPORATION

This document shall not be duplicated, nor its contents used

for any purpose, unless express permission has been granted in advance.

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ALPHI TECHNOLOGY CORP. Page iii Ver 1.1

Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

TABLE OF CONTENTS

1. GENERAL DESCRIPTION_______________________________________________1

1.1 INTRODUCTION__________________________________________________________1

1.2 FUNCTIONAL DESCRIPTION _______________________________________________1

1.3 REFERENCE MATERIALS LIST _____________________________________________5

2. HOST (CPCI) SIDE ____________________________________________________6

2.1 CPCI CONFIGURATION REGISTERS _________________________________________6

2.2 CPCI BASE ADDRESS REGISTERS__________________________________________6

2.3 CPCI OPERATION REGISTERS _____________________________________________6

3. C31 SIDE ____________________________________________________________7

3.1 INTERNAL ORGANIZATION ________________________________________________7

3.2 CPCI INTERFACE ________________________________________________________7

3.3 DUAL PORT MEMORY_____________________________________________________8

3.4 IP INTERFACE and PAGED MEMORY ________________________________________9

3.5 DSP MEMORY AND REGISTER MAP SUMMARY________________________________9

3.6 RESET SIGNALS ________________________________________________________12

3.7 LOCAL DSP INTERRUPT SOURCES ________________________________________12

4. JUMPER DESCRIPTIONS______________________________________________13

5. LED INDICATORS____________________________________________________14

6. CONNECTIONS______________________________________________________14

6.1 IP I/O CONNECTORS_____________________________________________________14

6.2 SERIAL RS232 PORT (P4) ________________________________________________14

6.3 SERIAL RS422 / RS485 PORT (P3) _________________________________________15

6.4 DSP SERIAL PORT (P15) _________________________________________________16

6.5 EMULATOR CONNECTION (P17) ___________________________________________16

6.6 32 BIT CPCI BUS (J1) ____________________________________________________16

6.7 Backplane I/O Connections (J4 and J5) _____________________________________16

6.8 FACTORY USE (P16)_____________________________________________________21

7. STANDALONE OPERATION ___________________________________________21

7.1 CPCI RESET ___________________________________________________________21

7.2 CPCI BUS CLOCK _______________________________________________________21

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Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

1. GENERAL DESCRIPTION

1.1 INTRODUCTION

The CPCI-QIPC is a CPCI expansion card in a 6U form factor. The CPCI-QIPC provides

mechanical support and the electrical interfaces for four single width IP modules, or two

double width IP modules. Multiple CPCI-QIPC boards may be installed in a single system.

The primary features of the CPCI-QIPC are as follows:

•Support for up to four IP modules

•8 MHz or 32 MHz IP operation via jumper selection

•On board DSP C31 to offload I/O operation from host or standalone applications

•Direct memory mapped control of DSP from CPCI bus via AMCC 5933 PCI Chip

•Direct dual ported memory access from CPCI bus and C31 (up to 4 Mbytes)

•Full interrupt support of host and DSP C31

•Supports double-wide form factor IndustryPack

•Front panel I/O connectors for all IPs

1.2 FUNCTIONAL DESCRIPTION

A functional block diagram of the CPCI-QIPC is presented below in Figure 1-1. The jumper

placement is depicted in Figure 1-2 and the connector placement in Figure 1-3. The CPCI-

QIPC can operate as a slave that is managed by the host processor on the CPCI bus or it

can operate in a standalone mode of operation without a host. The IP modules share a

common clock that can be jumpered for 8 or 32 MHz operation. Each pair of single width

IPs, or each double width IP is individually selectable as to clock rate.

The CPCI-QIPC is supported by ALPHI Technology under Windows NT by a Board

Support Package which is supplied with the card. Other documentation supplied with the

card will describe this support in full detail.

The card is also supported by a DSP Support Library providing the following features:

•Common access routines for communications with the host

•Mapping C language standard input and output by the DSP to the onboard 8530 serial

chip

•Identify the applicable card resources and parameters

All these are provided in a manner consistent across ALPHI Technology platforms. Other

documentation supplied with the card will describe the support in full detail.

A bootloader provided on the card allows for control by the HOST and for independent

operation in stand alone operation. User code can be downloaded to FLASH memory and

booted automatically on reset. Access to the card can be made both by the HOST CPCI

bus and serially through the 8530.

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Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

PCI to Local Bus

Bridge

Mailbox Registers

DSP C31

32 MHz

Local SRAM

128K x 32

Local FLASH

128K x 8 or

512K x 8

Local EPROM

(Boot)

512K x 8

IP A

IP B IP D

IP C

Dual Ported SRAM

1M x 32

Dual Port

Arbitration

Connector Connector

ConnectorConnector

Dual Port

Bus Local Bus

Pass Thru Buffers

PCI

Bus

SCC8530

Serial Port

Figure 1.1: Block Diagram

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Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

IP A

IP C

IP B

IP D

W8 W9

W10

W11

W13

W12

W14

W16

W15

Figure 1.2: Jumper Locations

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Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

IP A

IP C

IP B

IP D

Figure 1.3: Connector Locations

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Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

1.3 REFERENCE MATERIALS LIST

The reader should refer to the PCI Local Bus Specification for a detailed explanation of the

PCI bus architecture and timing requirements. This specification is available from the

following source:

PCI Special Interest Group

PO Box 14070

Portland, OR 97214

Tel: (800) 433-5177

Tel: (503) 797-4207

Fax: (503) 234-6762

The reader is also referred to the S5933 PCI Controller data book:

AMCC Applied Micro Circuits Corporation

6195 Lusk Boulevard

San Diego, CA 92121-2793

Tel: (800) 755-2622

http://www.amcc.com

WindowsNT and Windows95 Programming Tools:

BlueWater Systems

144 Railroad Ave. Suite #217

Edmonds, WA 98020

Tel: (206) 771-3610

Fax: (206) 771-2742

E-Mail: [email protected]

Web: http://www.bluewatersystems.com

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Part Number : 739-11-000-4000 Copyright ALPHI Technology Corporation ,1998

2. HOST (CPCI) SIDE

2.1 CPCI CONFIGURATION REGISTERS

The card presents the following configuration values to the CPCI system, based on the

values stored in the NVRAM device read by the AMCC PCI interface chip.

Vendor ID 0x13c5 (ALPHI Technology)

Device ID 0x0201 (CPCI-QIPC)

Revision ID 0x00

Class Code 0xff0000 (Device does not fit into defined class codes)

Interrupt Line 0xff

Interrupt Pin A

Multifunction Device No

Build In Self Test No

Latency Timer 0x00

Minimum Grant 0x00

Maximum Latency 0x00

Expansion ROM Size None

Table 2.1: PCI Configuration Registers

2.2 CPCI BASE ADDRESS REGISTERS

The card requests base address regions from the CPCI system after RESET, based on the

values stored in the NVRAM device read by the AMCC PCI interface chip.

The decode addresses of these regions are assigned by the host processor. The CPCI-

QIPC uses 3 of the 5 AMCC mapped base address registers. The AMCC is normally

programmed at the factory to request the following resources from the CPCI BIOS:

BASE

BAR From To Description Type

00x00000000 0x00000003F AMCC PCI Operation Registers MEM

10x00000000 0x00FFFFFF Reserved for future use MEM

30x00000000 0x003FFFFF Dual Port Memory MEM

30x00400000 0x01FFFFFF Reserved for future use MEM

Table 2.2: Base Addresses and Use

NOTE: The AMCC has been programmed to request memory above 1 Mbytes.

2.3 CPCI OPERATION REGISTERS

The host processor communicates with the CPCI-QIPC module via the AMCC pass-through

interface. After the base address registers have been programmed by the CPCI

configurator, incoming CPCI I/O or Memory cycles are translated into either accesses to the

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AMCC chip or to the Dual Port SRAM. The PCI Operation Registers of the AMCC 5933 chip

are depicted below:

Offset Register Name

0x00 OMB1 Outgoing Mailbox Register 1

0x04 OMB2 Outgoing Mailbox Register 2

0x08 OMB3 Outgoing Mailbox Register 3

0x0C OMB4 Outgoing Mailbox Register 4

0x10 IMB1 Incoming Mailbox Register 1

0x14 IMB2 Incoming Mailbox Register 2

0x18 IMB3 Incoming Mailbox Register 3

0x1C IMB4 Incoming Mailbox Register 4

0x20 FIFO Register Port (bi-directional)

0x24 MWAR Master Write Address Register

0x28 MWTC Master Write Transfer Counter

0x2C MRAR Master Read Address Register

0x30 MRTC Master Read Transfer Counter

0x34 MBEF Mailbox Empty/Full Status

0x38 INTCSR Interrupt Control/Status Register

0x3C MCSR Bus Master Control/Status Register

Table 2.2: AMCC Registers (HOST)

For more information about these registers refer to the AMCC PCI controller manual.

3. C31 SIDE

3.1 INTERNAL ORGANIZATION

The CPCI-QIPC card is divided into different sections. Each section and its relationship to

other sections will be discussed. The CPCI-QIPC sections are:

•CPCI interface

•Dual Port Memory

•IP interface

3.2 CPCI INTERFACE

The local DSP processor communicates with the CPCI bus through the AMCCS9533 chip

that provides bi-directional FIFO and Mailbox registers. The CPCI-QIPC can function as

both a servant (CPCI target) or as a master (CPCI initiator) for DMA access. The following

interface descriptions refer to the CPCI interface as seen by the local DSP. The AMCC

registers are located at DSP address 0xf00080.

3.2.1 BI-DIRECTIONAL FIFO

Two separate FIFO data paths are implemented within the AMCCS9533, a read FIFO that

allows data transfers from the module to the CPCI bus and a write FIFO that transfers data

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