Cypress Semiconductor CY7C1345G Bedienungsanleitung

CY7C1345G

4-Mbit (128K x 36) Flow Through Sync SRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 38-05517 Rev. *E Revised July 15, 2007

Features

■128K x 36 common IO

■3.3V core power supply (VDD)

■2.5V or 3.3V IO supply (VDDQ)

■Fast clock-to-output times

❐6.5 ns (133 MHz version)

■Provide high performance 2-1-1-1 access rate

■User selectable burst counter supporting Intel Pentium inter-

leaved or linear burst sequences

■Separate processor and controller address strobes

■Synchronous self-timed write

■Asynchronous output enable

■Available in Pb-free 100-Pin TQFP package, Pb-free and

non-Pb-free 119-Ball BGA package

■ZZ Sleep Mode option

Functional Description

The CY7C1345G is a 128K x 36 synchronous cache RAM

designed to interface with high speed microprocessors with

minimum glue logic. The maximum access delay from clock rise

is 6.5 ns (133 MHz version). A two-bit on-chip counter captures

the first address in a burst and increments the address automat-

ically for the rest of the burst access. All synchronous inputs are

gated by registers controlled by a positive edge triggered Clock

Input (CLK). The synchronous inputs include all addresses, all

data inputs, address pipelining Chip Enable (CE1), depth

expansion Chip Enables (CE2and CE3), Burst Control inputs

(ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and

Global Write (GW). Asynchronous inputs include the Output

Enable (OE) and the ZZ pin.

The CY7C1345G enables either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses are initiated with the Processor

Address Strobe (ADSP) or the cache Controller Address Strobe

(ADSC) inputs.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) is active. Subsequent burst addresses

are internally generated as controlled by the Advance pin (ADV).

The CY7C1345G operates from a +3.3V core power supply

while all outputs operate with either a +2.5 or +3.3V supply. All

inputs and outputs are JEDEC standard JESD8-5 compatible.

For best practice recommendations, refer to the Cypress appli-

cation note AN1064, SRAM System Guidelines.

Selection Guide

Parameter 133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.0 ns

Maximum Operating Current 225 205 mA

Maximum Standby Current 40 40 mA

CY7C1345G

Document Number: 38-05517 Rev. *E Page 2 of 20

Logic Block Diagram

ADDRESS

BURST

COUNTER

AND LOGIC

CLR

ENABLE

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE

A[1:0]

DQ s

DQP

A0, A1, A

ADV

CLK

ADSP

ADSC

BWE

CE1

CE2

CE3

SLEEP

CONTROL

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

CY7C1345G

Document Number: 38-05517 Rev. *E Page 3 of 20

Pin Configurations

100-Pin TQFP Pinout

NC/72M

NC/36M

VSS

VDD

NC/9M

DQPB

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSP

100

BYTE A

BYTE C

ADV

ADSC

MODE

NC/18M

BYTE B

DQB

BYTE D

CY7C1345G

Document Number: 38-05517 Rev. *E Page 4 of 20

119-Ball BGA Pinout

Pin Configurations (continued)

2345671

VDDQ

NC/288M

NC/144M

DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

CE2A

DQC

VDDQ

DQC

VDDQ

DQD

VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

NCNCNCNC

NC/36MNC/72M

VDDQ

AAA

CE3

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

CY7C1345G

Document Number: 38-05517 Rev. *E Page 5 of 20

Pin Definitions

Name IO Description

A0, A1, A Input

Synchronous

Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LOW, and CE1,CE2, and CE3 are sampled active. A[1:0] feed

the two-bit counter.

BWA, BWB

BWC, BWD

Input

Synchronous

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW Input

Synchronous

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global

write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).

BWE Input

Synchronous

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted

LOW to conduct a byte write.

CLK Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

CE1Input

Synchronous

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE2and CE3to select or deselect the device. ADSP is ignored if CE1is HIGH. CE1is sampled only

when a new external address is loaded.

CE2Input

Synchronous

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE1and CE3to select or deselect the device. CE2 is sampled only when a new external address is

loaded.

CE3Input

Synchronous

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE1and CE2to select or deselect the device. CE3 is sampled only when a new external address is

loaded.

OE Input

Asynchronous

Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When

LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data

pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV Input

Synchronous

Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically incre-

ments the address in a burst cycle.

ADSP Input

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are

also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-

nized. ASDP is ignored when CE1is deasserted HIGH.

ADSC Input

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are

also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-

nized.

ZZ Input

Asynchronous

ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep

condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin

has an internal pull down.

DQs

DQPA, DQPB

DQPC, DQPD

Synchronous

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

by the addresses presented during the previous clock rise of the read cycle. The direction of the pins

is controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and

DQP[A:D] are placed in a tri-state condition.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the core of the device.

VDDQ IO Power

Supply

Power supply for the IO circuitry.

VSSQ IO Ground Ground for the IO circuitry.

CY7C1345G

Document Number: 38-05517 Rev. *E Page 6 of 20

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. Maximum access delay from the

clock rise (tCO) is 6.5 ns (133 MHz device).

The CY7C1345G supports secondary cache in systems using

either a linear or interleaved burst sequence. The interleaved

burst order supports Pentium and i486™ processors. The linear

burst sequence is suited for processors that use a linear burst

sequence. The burst order is user selectable and is determined

by sampling the MODE input. Accesses are initiated with either

the Processor Address Strobe (ADSP) or the Controller Address

Strobe (ADSC). Address advancement through the burst

sequence is controlled by the ADV input. A two-bit on-chip wrap

around burst counter captures the first address in a burst

sequence and automatically increments the address for the rest

of the burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to all

four bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.

Three synchronous Chip Selects (CE1, CE2, and CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1is

HIGH.

Single Read Accesses

A single read access is initiated when the following conditions

are satisfied at clock rise:

1. CE1, CE2, and CE3are all asserted active.

2. ADSP or ADSC is asserted LOW (if the access is initiated by

ADSC, the write inputs are deasserted during this first cycle).

The address presented to the address inputs is latched into the

address register and the burst counter or control logic and

presented to the memory core. If the OE input is asserted LOW,

the requested data is available at the data outputs a maximum

to tCDV after clock rise. ADSP is ignored if CE1is HIGH.

Single Write Accesses Initiated by ADSP

Single write access is initiated when the following conditions are

satisfied at clock rise:

1. CE1, CE2, and CE3are all asserted active

2. ADSP is asserted LOW.

The addresses presented are loaded into the address register

and the burst inputs (GW, BWE, and BWx) are ignored during this

first clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a

write) on the next clock rise, the appropriate data is latched and

written into the device. Byte writes are allowed. During byte

writes, BWAcontrols DQAand BWBcontrols DQB, BWCcontrols

DQC, and BWDcontrols DQD. All IOs are tri-stated during a byte

write. Since this is a common IO device, the asynchronous OE

input signal is deasserted and the IOs are tri-stated prior to the

presentation of data to DQs. As a safety precaution, the data

lines are tri-stated once a write cycle is detected, regardless of

the state of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are

satisfied at clock rise:

1. CE1, CE2, and CE3are all asserted active.

2. ADSC is asserted LOW.

3. ADSP is deasserted HIGH

4. The write input signals (GW, BWE, and BWx) indicate a write

access. ADSC is ignored if ADSP is active LOW.

The addresses presented are loaded into the address register

and the burst counter or control logic and delivered to the

memory core. The information presented to DQ[D:A] is written

into the specified address location. Byte writes are allowed.

During byte writes, BWAcontrols DQA, BWBcontrols DQB, BWC

controls DQC, and BWDcontrols DQD. All IOs and even a byte

write are tri-stated when a write is detected. Since this is a

common IO device, the asynchronous OE input signal is

deasserted and the IOs are tri-stated prior to the presentation of

data to DQs. As a safety precaution, the data lines are tri-stated

once a write cycle is detected, regardless of the state of OE.

MODE Input

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left

floating selects interleaved burst sequence. This is a strap pin and must remain static during device

operation. Mode Pin has an internal pull up.

NC No Connects. Not Internally connected to the die.

NC/9M,

NC/18M,

NC/36M

NC/72M,

NC/144M,

NC/288M,

NC/576M,

NC/1G

–No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,

NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the

die.

Pin Definitions (continued)

Name IO Description

CY7C1345G

Document Number: 38-05517 Rev. *E Page 7 of 20

Burst Sequences

The CY7C1345G provides an on-chip two-bit wrap around burst

counter inside the SRAM. The burst counter is fed by A[1:0] and

follows either a linear or interleaved burst order. The burst order

is determined by the state of the MODE input. A LOW on MODE

selects a linear burst sequence. A HIGH on MODE selects an

interleaved burst order. Leaving MODE unconnected causes the

device to default to a interleaved burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation sleep mode. Two clock cycles

are required to enter into or exit from this sleep mode. In this

mode, data integrity is guaranteed. Accesses pending when

entering the sleep mode are not considered valid nor is the

completion of the operation guaranteed. The device is

deselected prior to entering the sleep mode. CEs, ADSP, and

ADSC must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Table 1. Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Table 2. Linear Burst Address Table (MODE = GND)

First

Address

A1,A0

Second

Address

A1,A0

Third

Address

A1,A0

Fourth

Address

A1,A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 40 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

CY7C1345G

Document Number: 38-05517 Rev. *E Page 8 of 20

Truth Table

The truth table for CY7C1345G follows. [1, 2, 3, 4, 5]

Cycle Description Address

Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power

down

None H X X L X L X X X L-H Tri-State

Deselected Cycle, Power

down

None LLXLL XXXXL-HTri-State

Deselected Cycle, Power

down

None LXHLL XXXXL-HTri-State

Deselected Cycle, Power

down

None L L X L H L X X X L-H Tri-State

Deselected Cycle, Power

down

None X X X L H L X X X L-H Tri-State

Sleep Mode, Power down None X X X H X XXXXXTri-State

Read Cycle, Begin Burst External L H L L L X X X L L-H Q

Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

Write Cycle, Begin Burst External L H L L H L X L X L-H D

Read Cycle, Begin Burst External L H L L H L X H L L-H Q

Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

Read Cycle, Continue Burst Next X X X L H H L H L L-H Q

Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

ReadCycle,SuspendBurstCurrentXXXLH HHHHL-HTri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

ReadCycle,SuspendBurstCurrentHXXL X HHHHL-HTri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes

1. X = “Do Not Care,” H = Logic HIGH, and L = Logic LOW.

2. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA,

BWB, BWC, BWD), BWE, GW = H.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a “Do Not Care” for

the remainder of the write cycle.

5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive

or when the device is deselected, and all data bits behave as output when OE is active (LOW).

CY7C1345G

Document Number: 38-05517 Rev. *E Page 9 of 20

Truth Table for Read or Write

The partial truth table for read or write follows. [1, 6]

Function GW BWE BWDBWCBWBBWA

Read HHXXXX

Read H L H H H H

Write Byte (A, DQPA)HLHHHL

Write Byte (B, DQPB)HLHHLH

Write Bytes (B, A, DQPA, DQPB)HLHHLL

Write Byte (C, DQPC)HLHLHH

Write Bytes (C, A, DQPC, DQPA)HLHLHL

Write Bytes (C, B, DQPC, DQPB)HLHLLH

Write Bytes (C, B, A, DQPC, DQPB, DQPA)HLHLLL

Write Byte (D, DQPD) HL LHHH

Write Bytes (D, A, DQPD, DQPA)HLLHHL

Write Bytes (D, B, DQPD, DQPA)HLLHLH

Write Bytes (D, B, A, DQPD, DQPB, DQPA)HLLHLL

Write Bytes (D, B, DQPD, DQPB)HLLLHH

Write Bytes (D, B, A, DQPD, DQPC, DQPA)HLLLHL

Write Bytes (D, C, A, DQPD, DQPB, DQPA)HLLLLH

WriteAllBytes HLLLLL

WriteAllBytes LXXXXX

Note

6. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is done based on the active byte write.

CY7C1345G

Document Number: 38-05517 Rev. *E Page 10 of 20

Maximum Ratings

Exceeding the maximum ratings may shorten the battery life of

the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V

Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD

DC Voltage Applied to Outputs

in tri-state.............................................–0.5V to VDDQ + 0.5V

DC Input Voltage ................................... –0.5V to VDD + 0.5V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage

(MIL-STD-883, Method 3015) .................................. >2001V

Latch up Current..................................................... >200 mA

Operating Range

Range Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V

−5%/+10%

2.5V –5%

to VDD

Industrial –40°C to +85°C

Electrical Characteristics

Over the Operating Range [7, 8]

Parameter Description Test Conditions Min Max Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ IO Supply Voltage 2.375 VDD V

VOH Output HIGH Voltage for 3.3V IO, IOH = –4.0 mA 2.4 V

for 2.5V IO, IOH = –1.0 mA 2.0 V

VOL Output LOW Voltage for 3.3V, IO, IOL= 8.0 mA 0.4 V

for 2.5V IO, IOL = 1.0 mA 0.4 V

VIH Input HIGH Voltage for 3.3V IO 2.0 VDD + 0.3V V

for 2.5V IO 1.7 VDD + 0.3V V

VIL Input LOW Voltage[7] for 3.3V IO –0.3 0.8 V

for 2.5V IO –0.3 0.7 V

IXInput Leakage Current except

ZZ and MODE

GND ≤VI≤VDDQ −55µA

Input Current of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤VI≤VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply Current VDD = Max, IOUT = 0 mA,

f = fMAX= 1/tCYC

7.5 ns cycle, 133 MHz 225 mA

10 ns cycle, 100 MHz 205 mA

ISB1 Automatic CE Power down

Current—TTL Inputs

Max VDD, Device Deselected,

VIN ≥VIH or VIN ≤VIL, f = fMAX,

inputs switching

7.5 ns cycle, 133 MHz 90 mA

10 ns cycle, 100 MHz 80 mA

ISB2 Automatic CE Power down

Current—CMOS Inputs

Max VDD, Device Deselected,

VIN ≥VDD – 0.3V or VIN ≤0.3V,

f = 0, inputs static

All speeds 40 mA

ISB3 Automatic CE Power down

Current—CMOS Inputs

Max VDD, Device Deselected,

VIN ≥VDDQ – 0.3V or VIN ≤

0.3V, f = fMAX, inputs switching

7.5 ns cycle, 133 MHz 75 mA

10 ns cycle, 100 MHz 65 mA

ISB4 Automatic CE Power down

Current—TTL Inputs

Max VDD, Device Deselected,

VIN ≥VDD – 0.3V or VIN ≤0.3V,

f = 0, inputs static

All speeds 45 mA

Notes

7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

8. TPower up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ <VDD.

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