Digital Equipment PDP-11 Series Bedienungsanleitung

PDP-ll UNIBUS Processor Handbook

PDP-ll/84, PDP-ll/44, and PDP-ll/24

Digital Equipment Corporationmakes no representation

that

the

interconnec-

tion

its products in

the

mannerdescribedhereinwill notinfringe

existing

future patent rights,·nor

the descriptions contained herein imply the

granting

license to make, use,

sell equipment constructed in accordance

with this description.

Digital believes

the

information. in this publication

accurate

of its

publicationdate; such information

subject to change without notice. Digital

not responsible for any inadvertent errors.

The following are trademarks

Digital Equipment Corporation:

DEC,

DECnet, DECsystem-10, DECSYSTEM-20, DECtape,

DECUS,

DECwriter,

DlBOL, the Digital logo, lAS,

MASSBUS,

OMNIBUS,

PDp,

PDT,

Q-bus,

RSTS,

RSX,

RT-ll,

ULTRIX,

UNIBUS,

VAX,

VMS,

and

VT.

iii

Contents

Preface

.................................................

VII

Chapter 1 • Introduction

Overview of PDP-ll UNIBUS Family Members

...................

1-2

PDP-ll/84 System

........................................

1-3

Software

...............................................

1-6

Networks

...............................................

1-8

Peripherals

.............................................

1-8

Service

................................................

1-9

Documentation

..........................................

1-9

Chapter 2 •

PDP-ll/84

Introduction

............................................

2-2

Features

................................................

2-2

System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3

Central Processor

........................................

, 2-4

General Registers

......................................

2-6

Processor Status Word

..................................

2-7

Program Interrupt Request Register

.......................

2-10

Pipeline Processing

....................................

2-11

CPU

Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-12

Stack Limit Protection

.................................

2-13

Kernel Protection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-14

Trap and Interrupt Priorities

.............................

2-15

Hardware Detected Errors

..............................

2-16

Private Memory Interconnect

..............................

2-17

Memory System

.........................................

2-18

Memory Management

.................................

2-18

Error Correction Code

.................................

2-19

Battery Backup Unit

...................................

2-19

UNIBUS Adapter

(UBA)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-20

DMA

Cache

.........................................

2-20

UNIBUS Mapping

.....................................

2-21

Boot

ROM

Facility

....................................

2-21

Cache Memory

.......................................

2-22

Cache Registers

......................................

2-24

Backplane Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-28

Console Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-29

Console Serial Line Unit Registers

........................

2-29

Line-time Clock

.........................................

2-33

Clock status Register

...................................

2-33

Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-34

Setup Mode

.........................................

2-34

Program Mode

.......................................

2-36

Console ODT Mode

...................................

2-37

Specifications

..........................................

2-38

Chapter

PDP-ll/44

System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

Central Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

General Registers

......................................

3-4

Processor Status Word

..................................

3-5

CPU

Registers

...........................................

3-7

CPU

Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-7

Processor

Traps.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-9

Program Interrupt Request Register

.......................

3-11

CPU

and I/O Device Registers

and

Addresses

................

3-12

Memory Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-13

Error Correction Code and Battery Backup

.................

3-13

Memory Management

.................................

3-13

UNIBUS

Map

........................................

3-13

Cache Memory

.........................................

3-13

General System Architecture

............................

3-13

CPU

Bypass of the Cache

...............................

3-14

Cache Memory Organization

............................

3-15

Cache-Control Registers

................................

3-15

Floating-Point Processor

..................................

3-21

Backplane Configuration

..................................

3-21

Serial Line Unit Registers

..................................

3-21

Serial Line Unit Timing Considerations

....................

3-22

Terminal Serial Line Unit Control Registers

.................

3-22

Second Serial Line

Unit

Registers

(SLU

. . . . . . . . . . . . . . . . .

3-26

Line

Clock.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-29

Line Clock Status Register

..............................

3-29

Address andVector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . .

Specifications

..........................................

3-31

Chapter 4 •

PDP.ll/24

System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4·2

Central Processor

.........................................

4·2

Registers

...............................................

4·4

Processor Status Word

..................................

4-5

CPU Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Processor Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-8

CPU and I/O Device Registers and Addresses

.................

4-9

Memory System

.........................................

4-10

Memory Management

.................................

4·10

Error Correcting Code and Battery Backup

.................

4-10

UNIBUS

Map

........................................

4-10

Backplane Configuration

..................................

4-10

Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4·11

Program Mode

.......................................

4-12

Console

ODT

Mode

...................................

4-13

Address Specification

....................................

4-14

Processor I/O Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-14

Stack Pointer Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-14

Entering Octal Digits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-15

Serial Line Units

........................................

4-16

Terminal Serial Line Unit Control Registers

.................

4-16

Second Serial Line Unit Registers . . . . . . . . . . . . . . . . . . . . . . .

4-19

Line Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-22

Clock Status Register

..................................

4-22

Address and Vector Assignments

............................

4-23

Specifications

..........................................

4-23

Chapter 5 • UNIBUS Technical Description

Characteristics of the

UNIBUS

...............................

5-2

Nonmultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-2

Strict Master/Slave Relationship . . . . . . . . . . . . . . . . . . . . . . . . .

5·3

Partially Distributed

Arbitration.

. . . . . . . . . . . . . . . . . . . . . . . .

5-3

Overlapped Arbitration and Data Transfer

...

. . . . . . . . . . . . . .

5-5

Asynchronous Operation

................................

5-5

Address

Bits.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-7

Word or Byte Operations

................................

5-7

Parity Error Information from Slaves

.......................

5-7

UNIBUS

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-8

UNIBUS

Data

and Address Organization . . . . . . . . . . . . . . . . . . . . . . . 5·9

Types

UNIBUS

Data

Transfers

............................

Read Word

..........................................

5-11

Write Word

..........................................

5-12

Write Byte

..........................................

5-12

Read Word with Write

Intent

............................

5-13

Write Vector

.........................................

5-14

UNIBUS

Signal Details

....................................

5-14

Initialization and Shutdown Signals

.......................

5-17

Powerup Timing

......................................

5-18

Powerdown Timing

....................................

5-19

Initialization

Timing.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-20

Arbitration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-21

UNIBUS

Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-22

Abnormal Cycles

.....................................

5-23

Data Transfer Signals

..................................

5-25

DATI

Timing.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-27

DATIP

................................

.............

5-29

DAIDjDAIDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-29

Write Vector Timing

...................................

5-30

Abnormal Bus Cycles

..................................

5-32

Multiple Bus Cycles

....................................

5-32

Miscellaneous Signals

.................................

, 5-33

UNIBUS

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .

5-34

Electrically Bidirectional High-speed Lines

..................

5-35

Electrically Unidirectional High-speed Lines

.................

5-35

BUS

L and

BUS

...........................

5-36

Design Suggestions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-37

Watch

the

dc Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-37

Maintain 120-ohm Impedance and Watch

Signals

...........

5-38

Minimize Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-39

ConsiderAll Timing Cases

..............................

5-39

Be A

Good

Bus Citizen

.................................

5-40

Appendix A • PDP-ll Family Differences

Table

. . . . . . . . . . . . . . .

Appendix

B·

Console Commands. . . . . . . . . . . . . . . . . . . . . . . . .

B-1

Appendix C • Instruction Times

..............

;.............

C-l

Index.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index-l

vii

Preface

This handbook

a reference guide that focuses on Digital's PDP-ll

UNIBUS

processors and details the

UNIBUS

specifications. Written with both evalua-

tors and users in mind, this handbook will help you choose the processor

that

best meets the needs of your application.

Chapters 1through 4 supply a discussion

the key functions of the following

PDP-ll

UNIBUS

processors.

• PDP-ll/84

• PDP-ll/44

• PDP-ll/24

Chapter5 describes thetechnical specifications

the PDP-ll

UNIBUS

to assist

in configuring large, complex PDP-ll systems and to aid in the design of

interfaces for PDP-lls.

After reading this handbook, you may wish to learn more about PDP-ll

architecture.

The

PDP-ll Architecture Handbook

a companion to this

handbook and describes the

key

elements of thePDP-ll architecture, including

addressing modes, the PDP-ll instruction set, memory management, PDP-ll

floating point, commercial instruction set, and the assignment of addresses

and vectors. This and other handbooks

that

you can order are listed in the

documentation section

Chapter

A postage-paid Reader's Comments card

located at the back of this

handbook.

hope you will take the time to fill

out.

Your

suggestions will

help us to continue to present literature

that

meets your needs.

Chapter 1 •Introduction

Andere Handbücher für PDP-11 Series

Dieses Handbuch passt für folgende Modelle

Inhaltsverzeichnis

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Digital Equipment 300 Series AXP Leitfaden

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Digital Equipment VT 14 Bedienungsanleitung

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Digital Equipment M7142 Bedienungsanleitung

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Digital Equipment RK05 Series Bedienungsanleitung

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Digital Equipment Unibus VAX-11/780 Bedienungsanleitung

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Digital Equipment VAX 4000 Series Leitfaden

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Beliebte Computerhardware Handbücher anderer Marken

EMC2

EMC2 VNX Series Betriebsanleitung

Panasonic

Panasonic DV0PM20105 Bedienungsanleitung

Mitsubishi Electric

Mitsubishi Electric Q81BD-J61BT11 Bedienungsanleitung

Gigabyte

Gigabyte B660M DS3H AX DDR4 Bedienungsanleitung

Raidon

Raidon iT2300 Bedienungsanleitung

National Instruments

National Instruments PXI-8186 Bedienungsanleitung

Hauppauge

Hauppauge WinTV-HVR-2250 Bedienungsanleitung

Kontron

Kontron CP6002 Bedienungsanleitung

Manhattan

Manhattan 702843 Bedienungsanleitung

Aphex

Aphex 230 Bedienungsanleitung

Intel

Intel NUC 12 Pro Bedienungsanleitung

Galaxy

Galaxy GHDX2-2430S-24F4D Bedienungsanleitung

Intel

Intel AXXRMFBU4 Bedienungsanleitung

Kontron

Kontron DIMM-PC/MD Bedienungsanleitung

ST X-NUCLEO-SAFEA1B Betriebsanleitung

STEINWAY LYNGDORF

STEINWAY LYNGDORF SP-1 Bedienungsanleitung

Advantech

Advantech ASMB-935 Series Bedienungsanleitung

Jupiter

Jupiter RAM PACK Bedienungsanleitung