Dynamic Engineering PCIe 8L XMC X1 Bedienungsanleitung

DYNAMIC ENGINEERING

150 Dubois St. Suite C, Santa Cruz, CA 95060

831-457-8891 Fax 831-457-4793

http://www.dyneng.com

[email protected]

Est. 1988

User Manual

PCIe 8L XMC X1

PCIe 8 Lane XMC Compatible Carrier

Revision A2

Corresponding Hardware: Revision A/B

Fab number:10-2012-0601/2

Embedded Solutions Page 2

PCIe8LXMCX1

PCIe and XMC Compatible Carrier

Dynamic Engineering

150 Dubois St. Suite C

Santa Cruz, CA 95060

831457-8891

831457-4793 FAX

This document contains information of

proprietary interest to Dynamic Engineering. It

has been supplied in confidence and the

recipient, by accepting this material, agrees that

the subject matter will not be copied or

reproduced, in whole or in part, nor its contents

revealed in any manner or to any person except

to meet the purpose for which it was delivered.

Dynamic Engineering has made every effort to

ensure that this manual is accurate and

complete. Still, the company reserves the right to

make improvements or changes in the product

described in this document at any time and

without notice. Furthermore, Dynamic

Engineering assumes no liability arising out of

the application or use of the device described

herein.

The electronic equipment described herein

generates, uses, and can radiate radio

frequency energy. Operation of this equipment

in a residential area is likely to cause radio

interference, in which case the user, at his own

expense, will be required to take whatever

measures may be required to correct the

interference.

Dynamic Engineering’s products are not

authorized for use as critical components in life

support devices or systems without the express

written approval of the president of Dynamic

Engineering.

Connection of incompatible hardware is likely to

cause serious damage.

Other trademarks and registered trademarks are owned by their

respective manufactures.

Manual Revision A2 Revised 05/12/14

Embedded Solutions Page 3

Table of Contents

PRODUCT DESCRIPTION 5

Headers and TestPoints 6

DipSwitch Settings 7

Options 7

XMC Module Backplane IO Interface Pin Assignment 9

APPLICATIONS GUIDE 10

Interfacing 10

Construction and Reliability 11

Thermal Considerations 11

WARRANTY AND REPAIR 12

Service Policy 12

Out of Warranty Repairs 12

For Service Contact: 12

SPECIFICATIONS 13

ORDER INFORMATION 14

Embedded Solutions Page 4

List of Figures

FIGURE 1 PCIE8LXMCX1 PN4 INTERFACE STANDARD 9

Embedded Solutions Page 5

Product Description

PCIe8LXMCX1 is part of the Dynamic Engineering PCI and XMC Compatible family of

modular I/O components. PCIe8LXMCX1 adapts an XMC to one PCIe slot.

The PC is still a frequent host to embedded HW for development, and delivery. With

the PCIe bus overtaking PCI, XMC’s and PC’s with PCIe are becoming common. Use

PCIe8LXMCX1 to use your XMC in your PC using an x8 or x16 position.

Special features:

• Passive 8 lane Gen1/2 design

• Voltage monitors, each with LED’s on plus 12V, minus 12V, plus 5V, plus 3.3V

• 10A regulator for XMC 3.3V and 5V supplies

• Selection switch for VPWR [12V or 5V]. Option for hardwired 5V or 12V

• Front panel connector access through PCI bracket

• User IO [Pn4] available through one of two cable connectors (DIN IDC or SCSI II

compatible) Spare pins on SCSI connector can be shunt selected to power or

ground.

• Cooling cutout for increased airflow to XMC’s

• Optional Fan(s) for increased airflow

• JTAG programming support

• DIP switch to select global addressing on XMC’s

The PCIe8LXMCX1 is ready to use with the default settings. Just install the XMC onto

the PCIe8LXMCX1 and then into the system.

Embedded Solutions Page 6

Headers and TestPoints

J6 is used to select the VPWR source for position 0 and 1 respectively. When the

Shunt closes 1-2 – 12V is selected. With 2-3 closed 5V is selected. FET’s are used to

provide a low impedance path from the power supplies to VPWR for each position.

Options are in place on the PCB to allow hardwired selections for clients who prefer a

fixed voltage. The headers are not installed when the fixed voltage option is in place.

With pin 2 open VPWR will be open.

J12, 13, are used to select the bezel grounding option. 1-2 selects AC coupled, 2-3

selects DC coupled and open is open. J13 = PCIe Bezel. J12 = XMC bezel.

J1 is an optional header for SMB connection. Pin 1 is data and pin 2 is clock. Both are

pulled up. 3rd party tools can be used to see the “innards” of the XMC if the bus is in

use. Usually not needed but handy if you are doing development.

TP1, TP2 are optional JTAG header/pwr used to connect to the XMC. .025” sq post

header. The pin definitions are in the silk. 1: 3.3V, 2: GND, 1: TMS, 2: TDO, 3: TDI, 4:

TCK, 5: TRST

J2 controls the voltage on 33,67 of P2 when the SCSI connector options are selected.

1-2 selects 3.3V and 2-3 selects ground on those pins. The shunt and traces are rated

for 1A. Not fuse protected.

J3 controls the voltage on 34,68 of P2 when the SCSI connector options are selected.

1-2 selects 3.3V and 2-3 selects ground on those pins. The shunt and traces are rated

for 1A. Not fuse protected.

P3 is an optional power connector to allow for added 12V power to be used by the

PCIe8LXMCX1. The PCIe gold fingers allow for about 60W of power to be consumed

by the board across all XMC voltages including power supply losses. In many cases

the power budget is more than sufficient. If your XMC requires more power please

request the optional power connectors [2x3 PC power cable common with current PC

Power supplies] to increase the 12V available. Both 12V entry points are diode coupled

to prevent the current back-feeding when an external or other supply is added.

P3: 1-3 = +12, 4-6 = GND.

Embedded Solutions Page 7

DipSwitch Settings

Switch 1: Global Address Settings

Position 1-3 corresponds to XMC GA0-2. When closed the signal is ‘0’. When open the

signal is ‘1’.

Position 4 corresponds to XMC-MVR0. When closed the signal is ‘0’. When open the

signal is ‘1’.

Position 5-8 are spare

Options

Dynamic Engineering offers multiple versions of the PCIe8LXMCX1design.

In addition to the basic passive design there are options for Ethernet, Fan, Serial ports,

and minimization.

The PCIe8LXMCX1 features cooling cutouts designed to support the addition of a fan in

one or two positions for each XMC. On PrXMC's and other XMC’s with high thermal

loads the fan option is a good idea. On cards with a lower thermal profile the fan is not

needed. The fan produces 5 CFM in a small area to create a high LFM rating suitable

for most cooling requirements. The fan used has a relatively low noise rating for quiet

operation. Position 1 is closest to the PCI bezel and position 2 is closer to the XMC

connectors.

In addition the PCIe8LXMCX1 has two options for Pn4 signal routing. VME style 2x32

pin header [shown] or a SCSI style connector.

Please mix and match options, as you need them.

Embedded Solutions Page 8

The “VME” connectors are oriented as shown in the photo on the cover, and the

diagram. The square pad in the photo is “A1”. The mating part number is 120-964-455

Panduit, DIN-IDCA-64CSB-TG30 Robinson Nugent, Berg also has a part which is

slightly taller.

Cables and breakouts are available from Dynamic Engineering – Please see DINterm64

and DINribn64 or HDEcabl68 and HDEterm68 products from the Dynamic Engineering

website.

Embedded Solutions Page 9

XMC Module Backplane IO Interface Pin Assignment

The figure below gives the pin assignments for the XMC Module IO Interface – from

Pn4 to the PCIe8LXMCX1connectors. Also see the User Manual for your XMC board for

more information. Please note that P2 or P3, P4 or P5 are installed not both.

DIN IDC [P13] SCSI II [P2] Pn4

A1 C1 1 35 3 1

A2 C2 2 36 4 2

A3 C3 3 37 7 5

A4 C4 4 38 8 6

A5 C5 5 39 11 9

A6 C6 6 40 12 10

A7 C7 7 41 15 13

A8 C8 8 42 16 14

A9 C9 9 43 19 17

A10 C10 10 44 20 18

A11 C11 11 45 23 21

A12 C12 12 46 24 22

A13 C13 13 47 27 25

A14 C14 14 48 28 26

A15 C15 15 49 31 29

A16 C16 16 50 32 30

A17 C17 17 51 35 33

A18 C18 18 52 36 34

A19 C19 19 53 39 37

A20 C20 20 54 40 38

A21 C21 21 55 43 41

A22 C22 22 56 44 42

A23 C23 23 57 47 45

A24 C24 24 58 48 46

A25 C25 25 59 51 49

A26 C26 26 60 52 50

A27 C27 27 61 55 53

A28 C28 28 62 56 54

A29 C29 29 63 59 57

A30 C30 30 64 60 58

A31 C31 31 65 63 61

A32 C32 32 66 64 62

33 67 Open, +3 or GND via J2,19 silk screen defined

34 68 Open, +3 or GND via J3,20

FIGURE 1 PCIE8LXMCX1 PN4 INTERFACE STANDARD

Read table:

P13-C1 = P2-35 = Pn4-1

P13-A1 = P2-1 = Pn4-3

etc.

Embedded Solutions Page 10

Applications Guide

Interfacing

Some general interfacing guidelines are presented below. Do not hesitate to contact the

factory if you need more assistance.

Installation

The XMC is mounted to the PCIe8LXMCX1 prior to installation within the chassis. For

best results: with the PCIe bracket installed, install the XMC at an angle so that the

XMC front panel bezel penetrates the PCIe bracket then rotate down to mate with the

XMC [PnX] connectors.

There are four mounting locations per XMC. Two into the XMC mounting bezel, and

two for the standoffs near the XMC bus connectors.

Start-up

Make sure that the "system" can see your hardware before trying to access it. Many

BIOS will display the PCI devices found at boot up on a "splash screen” with the

VendorID and CardId for the XMC installed and an interrupt level. If the information is

not available from the BIOS then a third party PCI device cataloging tool will be helpful

Watch the system grounds. All electrically connected equipment should have a fail-

safe common ground that is large enough to handle all current loads without affecting

noise immunity. Power supplies and power consuming loads should all have their own

ground wires back to a common point.

Power all system power supplies from one switch. Connecting external voltage to

the PCIe8LXMCX1 when it is not powered can damage it, as well as the rest of the host

system. This problem may be avoided by turning all power supplies on and off at the

same time. This applies more to the XMC’s installed onto the PCIe8LXMCX1 than the

PCIe8LXMCX1 itself, and it is smart system design when it can be achieved.

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