JYTEK PCIe-69529 Bedienungsanleitung

PCIe-69529

8-CH 24-Bit 204.8 kS/s

Dynamic Signal Acquisition Module

User’s Manual

Manual Rev.: 1.00

Revision Date: Jul.16,2016

Getting Service

SHANGHAI JYTEK Co., Ltd.

Web site: hp://www.jytek.com

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203

China

Tel: +86-21-5047-5899

Fax: +86-21-5047-5899

Email: [email protected]

Addional informaon, aids, and ps that help users perform tasks

Informaon to prevent minor physical injury, component damage, data loss,

and/or program corrupon when trying to complete a task.

Informaon to prevent serious physical injury, component damage, data loss,and/

or program corrupon when trying to complete a specic task.

This document contains proprietary informaon protected by copyright. All rights are

reserved. No part of this manual may be reproduced by any mechanical, electronic, or other

means in any form without prior wrien permission of the manufacturer. All specicaons

are subject to change without further noce.

Table of Contents

Geng Service �� I

1 Introducon�� 1

1�1 Features �� 1

1.2 Applicaons �� 1

1.3 Specicaons �� 2

1�3�1 Analog Input �� 2

1�3�2 Timebase �� 7

1�3�3 Triggers �� 8

1.3.4 General Specicaons �� 8

1.4 Schemacs and I/O �� 9

1.5 Soware Support ��11

1�5�1 SDK ��11

1�5�2 DSA-DASK��11

2 Geng Started��12

2�1 Package Contents ��12

2.2 Installaon Environment ��12

2�3 Installing the Module ��13

3 Operaons ��14

3.1 Funconal Block Diagram��14

3�2 Analog Input Channel��14

3.2.1 Analog Input Front-End Conguraon ��14

3�2�2 Input Range and Data Format��15

3�2�3 ADC and Analog Input Filter ��16

3�2�4 DMA Data Transfer��16

3�3 Trigger Source and Trigger Modes��18

3�4 Trigger Mode��20

3�5 ADC Timing Control ��22

3�5�1 Timebase ��22

3�5�2 DDS Timing vs� ADC��22

3�5�3 Filter Delay in ADC ��22

3.6 Synchronizing Mulple Modules ��23

3.6.1 SSI_TIMEBASE ��24

3�6�2 SSI_SYNC_START ��24

3�6�3 SSI_AD_TRIG ��24

Appendix A Calibraon��25

A.1 Calibraon Constant ��25

A.2 Auto-Calibraon ��25

Important Safety Instrucons��26

III

List of Tables

Table 1-1: Timebase�� 7

Table 1-2: Trigger Source & Mode �� 8

Table 1-3: Digital Trigger Input �� 8

Table 3-1: Input Range and Data Format ��15

Table 3-2: Input Range Midscale Values ��16

Table 3-3: ADC Sample Rates vs DDS Output Clock��16

Table 3-4: Preferred Characteriscs for Analog Triggers��20

Table 3-5: Timing Relaonship between ADC and PLL Clock ��22

Table 3-6: ADC Filter Delay��23

Table 3-7: SSI Timing Signal Denions ��23

List of Figures

Figure 1-1: Analog Input Channel Bandwidth, -1dBFS 108kS/s �� 5

Figure 1-2: Analog Input Channel Bandwidth, -1dBFS 108kS/s �� 5

Figure 1-3: Spurious Free Dynamic Range 54kS/s �� 6

Figure 1-4: Spurious Free Dynamic Range 108kS/s �� 6

Figure 1-5: Spurious Free Dynamic Range 192kS/s �� 7

Figure 1-6: PCIe-69529 Side View �� 9

Figure 1-7: PCIe-69529 I/O Array��10

Figure 3-1: Analog Input Architecture ��14

Figure 3-2: Linked List of PCI Address DMA Descriptors��17

Figure 3-3: Trigger Architecture��18

Figure 3-4: External Digital Trigger ��19

Figure 3-5: Analog Trigger Condions ��20

Figure 3-6: Post-Trigger Acquision��21

Figure 3-7: Delay Trigger Mode Acquision��21

Figure 3-8: Re-Trigger Mode Acquision ��22

Figure 3-9: Timebase Architecture ��22

Figure 3-10: SSI Architecture��24

1 Introduction

The PCIe-69529 is a high-performance 8-CH 24-Bit 204.8 kS/s dynamic signal acquision

module, specically designed for applicaons such as structural health monitoring, noise,

vibraon, and harshness (NVH) measurement, and phased array data acquision.

The PCIe-69529 features 24-bit simultaneous sampling at 204.8 kS/s over 8 channels,

and a 110 dB dynamic range, providing ample power for high-density, high channel count

signal measurement, and vibraon-opmized lower AC cuto frequency of 0.5 Hz. All input

channels incorporate 4 mA bias current for integrated electronic piezoelectric (IEPE) signal

condioning for accelerometers and microphones.

The PCIe-69529 is auto-calibrated with an onboard reference circuit calibrang oset and

acquiring analog input errors. Following auto-calibraon, the calibraon constant is stored

in EEPROM, such that these values can be loaded and used as needed by the board. There

is no requirement to calibrate the module manually.

1�1 Features

• PCI Express specicaon Rev. 1.1 compliant

• 8 simultaneous analog inputs

• 204.8 kS/s maximum sampling rate

• AC or DC input coupling, soware selectable

• Support for:

◦ One external digital trigger input

◦ IEPE output on each analog input, soware congurable

◦ Auto-calibraon

1�2 Applications

• Structural health monitoring

• Phase array data acquision

• Noise, vibraon, and harshness (NVH) detecon

• Machine status monitoring

1�3 Specifications

1�3�1 Analog Input

Channel Characteriscs

Channels 8

Type Dierenal or pseudo-dierenal

Coupling AC or DC, soware selectable

AC coupling cuto frequency 0.5Hz

ADC resoluon 24-Bit

ADC type Delta-sigma

Input signal range ±10V, ±1V

Sampling rate (FS) 8 kS/s to 204.8 kS/s,

768 μS/s increments for Fs > 108 kS/s,

576 μS/s increments for 54 kS/s ≤ Fs ≤108 kS/s

192 μS/s increments for 8KS/s≤ Fs ≤54kS/s

Over voltage protecon Dierenal:

±42.4V,

Pseudo-dierenal:

•posive terminal ±42.4 V

•negave terminal unprotected, rated at ±2.5 V

Input impedance 1MΩ, (50Ω between negave input and system ground for

pseudo-dierenal mode)

Oset error ±1 mV max.

Gain error ±0.1% of FSR

IEPE Current 4 mA, each channel independently soware congurable

IEPE Compliance 24V

System Noise

Sample Rate (kS/s) System Noise1 (LSBrms)1

Fs = 54 kS/s 37.4

Fs = 108 kS/s 66.5

Fs = 192 kS/s 74.6

1. Shorted input

Common Mode Rejecon Rao (CMRR)

Input Range (V) CMRR1 (dB)

±1V 65

±10V 80

1. Input frequency < 1 kHz

-3 dB Bandwidth

Sample rate1-3 dB bandwidth

Fs < 108 kS/s >0.4863 FS

Fs > 108 kS/s >0.22 FS

1. Disable digital lter when Fs < 108 kS/s; Enable digital lter when Fs > 108 kS/s

Flatness

Flatness (dB)1

Input Range (V) 54 kS/s

20 Hz to 22 kHz

108 kS/s

20 Hz to 45 kHz

192 kS/s

20 Hz to 42 kHz

±1V, ±10V 0.06 0.08 0.1

1. Relave to 1 kHz

Spurious Free Dynamic Range (SFDR)

SFDR (dBc)1,2

Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s

±1V, ±10V 104 104 105

1. 1 kHz input tone and -1 dBFS input amplitude.

2. Measurement Includes harmonics.

Dynamic Range

Dynamic Range (dBFS)1

Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s

±1V, ±10V 107 100 100

1. 1 kHz input tone and -60 dBFS input amplitude.

System to Noise Rao

SNR (dBc)1

Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s

±1V, ±10V 104 99 98

1. 1 kHz input tone and -1 dBFS input amplitude

Total Harmonic Distoron (THD)

THD (dBc)1

Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s

±1V -106 -106 -107

±10V -104 -104 -105

1. 1 kHz input tone and -1 dBFS input amplitude

Total Harmonic Distoron plus noise (THD+N)

THD+N (dBc)1

Input Range (V) 54 kS/s

20 Hz to 22 kHz

108 kS/s

20 Hz to 45 kHz

192 kS/s

20 Hz to 42 kHz

±1V -96 -94 -95

±10V -96 -92 -95

1. 1 kHz input tone and -1 dBFS input amplitude

Intermodulaon Distoron

IMD (dBc)1,2

Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s

±1V -103 -99 -99

±10V -105 -101 -101

1. CCIF 14 kHz + 15 kHz

2. -6 dBFS input amplitude for each tone

Crosstalk

Crosstalk (dBc)1,2

Input Range (V) 1 kHz 0.5 Fs

±1V, ±10V -100 -97

1. Shorted input

2. -1 dBFS input amplitude

Interchannel Gain Mismatch

Input Range (V) Gain Mismatch (dB)1

±1V, ±10V 0.1

1. 1 kHz input tone and -1 dBFS input amplitude

Interchannel Phase Mismatch

Input Range (V) Phase Mismatch (°)1

±1V, ±10V 1 khz 20 khz 86.4 khz

0.1 0.442 1.64

1. -1 dBFS input amplitude

Inhaltsverzeichnis

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